This topic is a little tricky. This falls under the category of what is design metrics. Like "how big is the chip?", "how fast is the chip?", "how much power does it consume?", etc. Sometimes people confuse design metrics on purpose in order to achieve their goals. So someone might say "transistor count" instead of "gate count" when describing the design if they want a bigger number.
As a designer, none of this should really matter to you much. I find that marketing and consumers tend to put more emphasis on these numbers.
As a designer, what I'm concerned about is how big the design is interms of slilicon aera (mm x mm) and how man standard cell parts, and which TYPE of standard cell parts my design uses.
So if someone asked me how big my design is, I'm usually talking to another engineer at my company or on my project. Then I tell them the estimate of the standard cell library instances.
If someone OUTSIDE the company asked me how big my design is. I tell them a very rough estimate of GATE counts, i.e. how many 2-input, 1x drive strength NAND gates the design might be equivalent to. So my disign might use 400k standard cell instances of all types and parts. Maybe even some special cells in the library that would have complex function. Then there are macros, memories and custom cells,etc. So the standard library parts may not be an accurate description of how the big or small the design is to an outsider because the design might be closer to 1.2 millin 2 input NAND gates.
It all depends on who your audience is and what type of information you are trying to communicate when you use terms like "standard cell library instance count" vs "raw gate count".
HTH