can anyone tell me how to estimate the delay of a clock tree for 500 register.
I have gated clock in my design which have a original clock A.
using dc, I create a clock for that clock B.
but how to set the delay of the clock B relative to clock A.
Or I should set the delay to 0,and I use the clock tree to make sure A and B change at the same phase?
I think you should gen clock tree in the backend tool, and then you gen sdf file , then you can check the phycial delay of two clock, and then you
can modify diffenrent clock domain phase, this is call ipo.
Just insert some equivalent level of dummy buffer cells . Leave them for backend guys to tune for balance. However you should know it's hard to balance the phase delay in difference clock domain for every corner cases .
can anyone tell me how to estimate the delay of a clock tree for 500 register.
I have gated clock in my design which have a original clock A.
using dc, I create a clock for that clock B.
but how to set the delay of the clock B relative to clock A.
Or I should set the delay to 0,and I use the clock tree to make sure A and B change at the same phase?
can anyone tell me how to estimate the delay of a clock tree for 500 register.
I have gated clock in my design which have a original clock A.
using dc, I create a clock for that clock B.
but how to set the delay of the clock B relative to clock A.
Or I should set the delay to 0,and I use the clock tree to make sure A and B change at the same phase?