Hi,Hi,
how does your setup look like by means of actual layout and connection to the cell?
Which IC is actually used? The schematic shows the LGS4054 and in the text you mention the LGS4056.
How does the handling look like when a damage occures, is it "reproduceable"?
According to the datasheet of the LGS4056 it seems it can widthsand ESD pulses according to the HBM and CDM, at least I would intreprete it like that. Unfortunately I could only find a chinese (?) datasheet. The VCC as well as the CE pin can handle voltages up to 28 V, so they should not be prone to EMC events "that-much". Or at least they can handle a "higher" voltage. Nevertheless, if using an USB wall-plug supply, disconnecting the supply may course high transients. You may place a TVS diode in the vicinity of the USB connector to limit this voltages e.g. SMAJ5.0A/AC.
The 10 µF capacitor at the input of VCC should be for sure large enough to eat up the charge introduced by ESD. Here, the effectiveness depends on the location of the capacitor. For ESD purposes it should be placed close to the USB connector especially befor splitting up into individual traces e.g. towards CE. Here the 10 µF is used as a buffer, and should be plced close to the VCC pin. You might place an additional 100 nF with a 100 V rating close to the USB connector.
The BAT pin has a maximum voltage rating of only 6 V, so also here the 10 µF capacitor should be more than sufficient to limit the voltage by an ESD event. What's the voltage rating of this capacitor? Also here, the capacitor should be placed close to the connector.
What you should keep in mind is the power dissipation of the IC, as you have set your charging current to 0.5 A. Starting at a VBAT volatage of ~2.75 V, a current of 500 mA is delivered (Figure 9 in the DS). With a supply voltage of 5 V, this would lead to a power loss of about (5 V - 2.75 V) • 0.5 A = 1.125 W. I could not find any information regarding the thermal resistance in the datasheet, but here you can find the junction-to-ambient information for a DFN 2x2 and 3x3. Depending on your used package, the temperature rise is quite high. I could not figure out if the LGS4056 also has a thermal regulation to protect itself. Also keep in mind, the thermal resistance stated in the link, as well as in every other datasheet is highly depending on the actual layout (effective copper area; VIAs; ....) and number of layers and of course if natural or forced convection is applied.
So please show us your design/layout and share the english datasheet if you have it for the CORRECT part number.
BR
Have you checked/protected for inductive flyback on Pogo Pins?
This is for sure the wrong datasheet. Have a look on the schematic in post #1 and compare the pins names. I linked a chinese datasheet in reply #2.
Here we have to differentiate ESD and EMC, where an ESD event usually represnts a high voltage (in the kV range) but with less energy. For testing, usually a capacitor in the low 100 pF range is charge up (kV) and discharged via a resistor in the 1 kOm range. By providing a large valued capacitor at the entrance of the PCB (connector), with a propper voltage rating, this will simply result in a low voltage at the DUT. Basically the charge at the DUT has to be the same as the one introduced by the ESD tester (gun) --> Q_ESD = Q_DUT --> V_DUT • C_DUT = V_ESD • C_ESD --> V_DUT = V_ESD • C_ESD / C_DUT.I don't know what ESD exposure you had, but this could be worse with more overvoltage energy.
To me it looks like the intention of the NTC is to protect the cell i.e. against thermal run-away. So it should be placed in the vicinity of the cell itself, but the battery holder is not located on the PCB. So a wired solution has to be used. For sure the NTC can be used in a way to protect the IC itself, or a smart combination of to do both, cell and IC. But as I'm not able to read the DS, I can not give any further advise on that.I suggest thermistor be included if there is no CC shutdown due to excessive battery leakage (>C/10) or shorted cell.
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