Analog ESD is not especially different from digital, other than that you care
more about leakage, through-resistance, etc. Since this is a project, how
about you begin with requirements as the pins see them (parasitics impact
and how much voltage excursion, to what return point, is allowable for a
reliable post-zap circuit. If you can enumerate these, the form may then be
obvious (or at least, which forms are unsuitable).
In a past life I had the joy of designing a 1kV HBM ESD protection for
60V analog pins. Ended up inventing a new structure and devices for it.
Probably outside the scope of a class project
but the point is, you
can't expect to find all of your answers in books. Sometimes you are
going to have to create a solution.
But many manufacturers' datasheets show pin network details and you
might chase after ICs that bear a resemblance to your target and see
what other people have decided, works.