Errors when simulating System Generator code in ModelSim

[kretzschmar]

Hello,

I generated a vhdl code using system generator...and simulated it successfully on Xilinx ISE...but i want to see the analog waveform...thus i tried to simulate using modelsim..(PS* i compiled xilinx libraries)....but i had these error :S

* Error: (vsim-3193) Load of "F:\Xilinx9.1\smartmodel\nt\installed_nt/lib/pcnt.lib/swiftpli_mti.dll" failed: DLL dependent library not found.
# ** Error: (vsim-PLI-3002) Failed to load PLI object file "F:\Xilinx9.1\smartmodel\nt\installed_nt/lib/pcnt.lib/swiftpli_mti.dll".

# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./pn_behavioral.do PAUSED at line 12

Plz helppppp...best regards


here's all the transcript:

# Reading F:/Xilinx9.1/ModelSim/tcl/vsim/pref.tcl
# // ModelSim SE 6.2b Jul 31 2006
# //
# // Copyright 2006 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# do {pn_behavioral.do}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package vcomponents
# -- Compiling entity accumulator_virtex2p_7_0_76a51e66155a8dd2
# -- Compiling architecture accumulator_virtex2p_7_0_76a51e66155a8dd2_a of accumulator_virtex2p_7_0_76a51e66155a8dd2
# -- Loading package prims_constants_v7_0
# -- Loading package prims_utils_v7_0
# -- Loading package numeric_std
# -- Loading package textio
# -- Loading package c_addsub_v7_0_comp
# -- Loading package c_reg_fd_v7_0_comp
# -- Loading entity c_accum_v7_0
# -- Compiling entity adder_subtracter_virtex2p_7_0_ccb483de4e9d85a2
# -- Compiling architecture adder_subtracter_virtex2p_7_0_ccb483de4e9d85a2_a of adder_subtracter_virtex2p_7_0_ccb483de4e9d85a2
# -- Loading entity c_addsub_v7_0
# -- Compiling entity sine_cosine_look_up_table_virtex2p_5_0_43a10a09e9f3a9b6
# -- Compiling architecture sine_cosine_look_up_table_virtex2p_5_0_43a10a09e9f3a9b6_a of sine_cosine_look_up_table_virtex2p_5_0_43a10a09e9f3a9b6
# -- Loading package math_real
# -- Loading package iputils_std_logic_arith
# -- Loading package iputils_std_logic_unsigned
# -- Loading package c_shift_fd_v7_0_comp
# -- Loading package c_sin_cos_v5_0_pack
# -- Loading package pipe_bhv_v5_0_comp
# -- Loading entity c_sin_cos_v5_0
# -- Compiling package conv_pkg
# -- Compiling package body conv_pkg
# -- Loading package conv_pkg
# -- Compiling package clock_pkg
# -- Loading package conv_pkg
# -- Compiling entity srl17e
# -- Compiling architecture structural of srl17e
# -- Compiling entity synth_reg
# -- Compiling architecture structural of synth_reg
# -- Compiling entity synth_reg_reg
# -- Compiling architecture behav of synth_reg_reg
# -- Compiling entity single_reg_w_init
# -- Compiling architecture structural of single_reg_w_init
# -- Compiling entity synth_reg_w_init
# -- Compiling architecture structural of synth_reg_w_init
# -- Compiling entity xlaccum
# -- Compiling architecture behavior of xlaccum
# -- Loading package std_logic_arith
# -- Compiling entity xladdsub
# -- Compiling architecture behavior of xladdsub
# -- Compiling entity lfsr_46c831df02
# -- Compiling architecture behavior of lfsr_46c831df02
# -- Loading entity synth_reg_w_init
# -- Compiling entity xlsincos
# -- Compiling architecture behavior of xlsincos
# -- Compiling entity slice_94e90fe469
# -- Compiling architecture behavior of slice_94e90fe469
# -- Compiling entity slice1_351c734db3
# -- Compiling architecture behavior of slice1_351c734db3
# -- Compiling entity ncosysgen
# -- Compiling architecture structural of ncosysgen
# -- Loading entity xlaccum
# -- Loading entity xladdsub
# -- Loading entity lfsr_46c831df02
# -- Loading entity xlsincos
# -- Loading entity slice_94e90fe469
# -- Loading entity slice1_351c734db3
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Loading package clock_pkg
# -- Compiling entity xlclkprobe
# -- Compiling architecture behavior of xlclkprobe
# -- Loading package vcomponents
# -- Compiling entity xlclockdriver
# -- Compiling architecture behavior of xlclockdriver
# -- Compiling entity ncosysgen_clock_driver
# -- Compiling architecture structural of ncosysgen_clock_driver
# -- Loading entity xlclockdriver
# -- Compiling entity ncosysgen_cw
# -- Compiling architecture structural of ncosysgen_cw
# -- Loading entity xlclkprobe
# -- Loading entity ncosysgen_clock_driver
# -- Loading entity ncosysgen
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package vcomponents
# -- Loading package numeric_std
# -- Loading package conv_pkg
# -- Compiling entity xlclk
# -- Compiling architecture behavior of xlclk
# -- Loading package clock_pkg
# -- Loading package textio
# -- Compiling entity xltbsource
# -- Compiling architecture behavior of xltbsource
# -- Loading package std_logic_arith
# -- Compiling entity xltbsink
# -- Compiling architecture behavior of xltbsink
# -- Compiling entity ncosysgen_tb
# -- Compiling architecture structural of ncosysgen_tb
# -- Loading entity xlclk
# -- Loading entity xltbsource
# -- Loading entity xltbsink
# -- Loading entity ncosysgen_cw
# vsim -L work -t ps ncosysgen_tb
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.
# ** Warning: [1] (vopt-3473) Component instance "persistentdff_inst : xlpersistentdff" is not bound.
# Loading F:\Xilinx9.1\smartmodel\nt\installed_nt/lib/pcnt.lib/swiftpli_mti.dll
# ** Error: (vsim-3193) Load of "F:\Xilinx9.1\smartmodel\nt\installed_nt/lib/pcnt.lib/swiftpli_mti.dll" failed: DLL dependent library not found.
# ** Error: (vsim-PLI-3002) Failed to load PLI object file "F:\Xilinx9.1\smartmodel\nt\installed_nt/lib/pcnt.lib/swiftpli_mti.dll".
# Region: /
# Loading f:\xilinx9.1\ModelSim\win32/../std.standard
# Loading f:\xilinx9.1\ModelSim\win32/../ieee.std_logic_1164(body)
# Loading f:\xilinx9.1\ModelSim\win32/../ieee.numeric_std(body)
# Loading work.conv_pkg(body)
# Loading F:\Xilinx9.1\VHDL\ModelSim\unisim.vcomponents
# Loading work.clock_pkg
# Loading f:\xilinx9.1\ModelSim\win32/../std.textio(body)
# Loading f:\xilinx9.1\ModelSim\win32/../ieee.std_logic_arith(body)
# Loading work.ncosysgen_tb(structural)#1
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./pn_behavioral.do PAUSED at line 12

 

[echo47]

modelsim error loading design

Here's a discussion about that same error message (search for the word "dll"):
http://forums.xilinx.com/xlnx/board/message?board.id=EDK&thread.id=786
The reply appears to have solved the problem.
The discussion concerns EDK and not System Generator, but maybe it will still be helpful.

 

[benlap]

error loading design modelsim

Hi All,

I also generated code in system generator and it synthesized fine in Xilinx ISE. I want to simulate the design in Modelsim (I compiled the xilinx libraries), but I had these errors:

# ** Error: ... 'clock_pkg' is not a library or a package.
# ** Error: ... VHDL Compiler exiting
# ** Error: C:/modeltech_6.4c/win32/vcom failed

I had a similar error with conv_pkg but I was able to find the package (conv_pkg.vhd) in the \Xilinx\10.1\DSP_Tools\sysgen\hdl directory. Also, in that directory is clock_pkg.v, but the above error persists even when I add the "clock_pkg.v" to my work folder.

I include the files with the following commands:
vcom -work work $SIM/conv_pkg.vhd
vlog +acc $SIM/clock_pkg.v

It looks like kretzschmar got futher than I did, so my question is: kretzschmar, how did you include clock_pkg successfully? Help would be much appreciated. Thanks!