anoop12
Member level 5
Hi all,
I need vhdl code for counter 74192( dual clock synchronous ).
I have written the code as below.
When I simulate it for upcounting or downcounting individually i.e. with only one process at a time, it works fine. But with two processes at a time it gives no output .
can anyone correct it?
here is the code
----------------------------------------------------------------------------------------
-- TI_UD_192.vhd
-- IC 74192 Decade Counter
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
------------------------------------------------------------------------------------------------------------------------------------------------------------
entity DECADE_COUNTER is
port ( I_P: in std_logic_vector(3 downto 0); -- input
I_UP:in std_logic; -- up-counting clock
I_DOWN: in std_logic; -- down-counting clock
I_CLR: in std_logic; -- Asynchronous Clear
I_load_N:in std_logic; --load to BCD 7,active low(Preset)
O_Q: out std_logic_vector(3 downto 0); -- output
O_B_N: out std_logic; - down counting borrow pulse
O_C_N: out std_logic); - up counting carry pulse
end DECADE_COUNTER;
--------------------------------------------------------------------------------------------------------------------------------------------------------------
architecture BEHAV of DECADE_COUNTER is
signal COUNT:std_logic_vector(3 downto 0);
begin
-- process for up counting
----------------------------------------------------------------------------------------------------------------------------------------------------------------
process(I_UP,I_CLR)
begin
if (I_CLR='1') then count<="0000";
elsif ( I_UP'event and I_UP='1') then
if(I_LOAD_N='0') then count<=I_P;
else count<=count + 1;
end if;
if (count="1001") then count<="0000";
end if;
end if;
end process;
-------------------------------------------------------------------------------------------------------------------------------------------------------------------
O_C_N<='0' when count="1001" else'1';
--process for down counting
------------------------------------------------------------------------------------------------------------------------------------------------------------------
process(I_DOWN,I_CLR)
begin
if (I_CLR='1') then count<="0000";
elsif ( I_DOWN'event and I_DOWN='1') then
if(I_LOAD_N='0') then count<=I_P;
count<=count-1;
end if;
if (count="0000") then count<="1001";
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
O_B_N<='0' when count="0000" else'1';
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
O_Q<= count ;
end BEHAV;
--------------------------
I need vhdl code for counter 74192( dual clock synchronous ).
I have written the code as below.
When I simulate it for upcounting or downcounting individually i.e. with only one process at a time, it works fine. But with two processes at a time it gives no output .
can anyone correct it?
here is the code
----------------------------------------------------------------------------------------
-- TI_UD_192.vhd
-- IC 74192 Decade Counter
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
------------------------------------------------------------------------------------------------------------------------------------------------------------
entity DECADE_COUNTER is
port ( I_P: in std_logic_vector(3 downto 0); -- input
I_UP:in std_logic; -- up-counting clock
I_DOWN: in std_logic; -- down-counting clock
I_CLR: in std_logic; -- Asynchronous Clear
I_load_N:in std_logic; --load to BCD 7,active low(Preset)
O_Q: out std_logic_vector(3 downto 0); -- output
O_B_N: out std_logic; - down counting borrow pulse
O_C_N: out std_logic); - up counting carry pulse
end DECADE_COUNTER;
--------------------------------------------------------------------------------------------------------------------------------------------------------------
architecture BEHAV of DECADE_COUNTER is
signal COUNT:std_logic_vector(3 downto 0);
begin
-- process for up counting
----------------------------------------------------------------------------------------------------------------------------------------------------------------
process(I_UP,I_CLR)
begin
if (I_CLR='1') then count<="0000";
elsif ( I_UP'event and I_UP='1') then
if(I_LOAD_N='0') then count<=I_P;
else count<=count + 1;
end if;
if (count="1001") then count<="0000";
end if;
end if;
end process;
-------------------------------------------------------------------------------------------------------------------------------------------------------------------
O_C_N<='0' when count="1001" else'1';
--process for down counting
------------------------------------------------------------------------------------------------------------------------------------------------------------------
process(I_DOWN,I_CLR)
begin
if (I_CLR='1') then count<="0000";
elsif ( I_DOWN'event and I_DOWN='1') then
if(I_LOAD_N='0') then count<=I_P;
count<=count-1;
end if;
if (count="0000") then count<="1001";
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
O_B_N<='0' when count="0000" else'1';
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
O_Q<= count ;
end BEHAV;
--------------------------