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| module testbench();
reg clock,reset,lnc;
reg [7:0] preload;
wire [7:0] count;
counter i_counter (clock,count,lnc,preload,reset);
initial
begin
$monitor ("clock=%b,reset=%b,preload=%d,lnc=%b,count=%d", clock,reset,preload,lnc,count);
clock = 1'b0;
lnc = 1'b0;
#525 lnc = 1'b1;
#100 lnc = 1'b0;
#400 lnc = 1'b1;
#100 lnc = 1'b0;
end
initial
begin
preload = 8'd0;
#1025 preload = 8'b11001010;
end
initial
begin
reset = 1'b1;
#125 reset = 1'b0;
end
always
#50 clock = ~clock;
initial
#2000 $finish;
endmodule |