Errors for identically port sizes for a simple counter simulation

[turbofrank]

I try to go through a ModelSim Simulation with these appended "counter.v" and "testbench.v". Compling is fine, but starting Simulation gives me Errors about port sizes. The port sizes seems to me correct and I can see any problem about these. May you of an idea? Kind regards.

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module counter (clock,reset,preload,lnc,count);
    input clock,reset,lnc;
    input [7:0] preload;
    output [7:0] count;
    reg [7:0] count;
 
always @ (posedge clock or posedge reset)
    begin
        if (reset == 1)
        count = 0;
        else
        begin 
            if (lnc == 1)
                count = preload;
            else
                count = count +1;
        end
    end
endmodule

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module testbench();
    reg clock,reset,lnc;
    reg [7:0] preload;
    wire [7:0] count;
 
    counter i_counter (clock,count,lnc,preload,reset);
 
initial
begin
       
    $monitor ("clock=%b,reset=%b,preload=%d,lnc=%b,count=%d", clock,reset,preload,lnc,count);
      clock = 1'b0;
         lnc = 1'b0;
    #525 lnc = 1'b1;
    #100 lnc = 1'b0;
    #400 lnc = 1'b1;
    #100 lnc = 1'b0;
end
initial
begin
    preload = 8'd0;
    #1025 preload = 8'b11001010;
end
initial
begin
         reset = 1'b1;
    #125 reset = 1'b0;
end
always
    #50 clock = ~clock;
initial
    #2000 $finish;
endmodule

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Transcript Warnings

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Code Verilog - [expand]
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vsim work.testbench
# vsim work.testbench 
# Loading work.testbench
# Loading work.counter
# ** Warning: (vsim-3015) D:/Tutorial/cosimulation/testbench.v(6): [PCDPC] - Port size (1 or 1) does not match connection size (8) for port 'reset'. The port definition is at: D:/Tutorial/cosimulation/counter.v(1).
# 
#         Region: /testbench/i_counter
# ** Warning: (vsim-3015) D:/Tutorial/cosimulation/testbench.v(6): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'preload'. The port definition is at: D:/Tutorial/cosimulation/counter.v(1).
# 
#         Region: /testbench/i_counter
# ** Warning: (vsim-3015) D:/Tutorial/cosimulation/testbench.v(6): [PCDPC] - Port size (1 or 1) does not match connection size (8) for port 'lnc'. The port definition is at: D:/Tutorial/cosimulation/counter.v(1).
# 
#         Region: /testbench/i_counter
# ** Error: (vsim-3053) D:/Tutorial/cosimulation/testbench.v(6): Illegal output or inout port connection for "port 'count'".
# 
#         Region: /testbench/i_counter
# ** Warning: (vsim-3015) D:/Tutorial/cosimulation/testbench.v(6): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'count'. The port definition is at: D:/Tutorial/cosimulation/counter.v(1).
# 
#         Region: /testbench/i_counter
# Error loading design

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[achaleus]

you done positional mapping wrong..

do this
counter i_counter(clock,reset,preload,lnc,count);