ERROR:Xst:1534; 739; 1431 - errors were found

[toki_rnm]

The following errors were found .. plz help me correct them

ERROR:Xst:1534 - Sequential logic for node <count1> appears to be controlled by multiple clocks.
ERROR:Xst:739 - Failed to synthesize logic for signal <count1>.
ERROR:Xst:1431 - Failed to synthesize unit <clk_gnrtr> .

The code is as follows

library ieee;
use iee.std_logic_1164.all;
use ieee. std_logic_arith.all;

entity clk_gnrtr is
port ( clk,reset: in std_logic;
y,ale,z: inout std_logic);
end clk_gnrtr;

architecture behavioral of clk_gnrtr is

signal count: std_logic_vector(3 downto 0);
signal count1: std_logic_vector(3 downto 0);
signal count2: std_logic_vector(2 downto 0);
signal count3: std_logic_vector(6 downto 0);
begin

process(clk,reset)
begin

if reset = '1' then
count<="0000";
count1<="00000";
count2<="000";
count3<="0000000";
y<='0';
z<='0';

elsif rising_edge (clk) then
count<=count + 1;
count3<= count3 + 1;

if count = "1101" then -- time period for 40khz is 25us. therefore on and off periods are approximately 13 us.
count<="0000";
y<= not y;
end if;

if count3<= "1100100" then -- time period for 5khz is 200us. therefore on and off periods are 100 us.
count3<="0000000";
z<= not z;
end if;

if rising_edge then
count1<= count1 + 1;

if count = "1000" then
count1<= "0000";
ale<='1';
end if;
end if;

if ale = '1' then
count2<=count2+ 1;

if count2 = "101" then
count2 <="000";
ale<= '0';
end if;
end if;
end if;

end process;
end behavioral;

 

[kvingle]

Re: Correct the errors .

The following errors were found .. plz help me correct them

ERROR:Xst:1534 - Sequential logic for node <count1> appears to be controlled by multiple clocks.
ERROR:Xst:739 - Failed to synthesize logic for signal <count1>.
ERROR:Xst:1431 - Failed to synthesize unit <clk_gnrtr> .

The code is as follows

library ieee;
use iee.std_logic_1164.all;
use ieee. std_logic_arith.all;

entity clk_gnrtr is
port ( clk,reset: in std_logic;
y,ale,z: inout std_logic);
end clk_gnrtr;

architecture behavioral of clk_gnrtr is

signal count: std_logic_vector(3 downto 0);
signal count1: std_logic_vector(3 downto 0);
signal count2: std_logic_vector(2 downto 0);
signal count3: std_logic_vector(6 downto 0);
begin

process(clk,reset)
begin

if reset = '1' then
count<="0000";
count1<="00000";
count2<="000";
count3<="0000000";
y<='0';
z<='0';

elsif rising_edge (clk) then
count<=count + 1;
count3<= count3 + 1;

if count = "1101" then -- time period for 40khz is 25us. therefore on and off periods are approximately 13 us.
count<="0000";
y<= not y;
end if;

if count3<= "1100100" then -- time period for 5khz is 200us. therefore on and off periods are 100 us.
count3<="0000000";
z<= not z;
end if;

if rising_edge then you cannot have this under rising_edge(clk)
count1<= count1 + 1;

if count = "1000" then
count1<= "0000";
ale<='1';
end if;
end if;

if ale = '1' then
count2<=count2+ 1;

if count2 = "101" then
count2 <="000";
ale<= '0';
end if;
end if;
end if;

end process;
end behavioral;

How can you wait to detect rising edge on signal y at the same instant when you have detected rising_edge on clk...
first visualize hardware on paper..then write code.

BTW what is y ?
do you want to use this signal as counter enable..?

 

[amraldo]

Re: Correct the errors .

You are assigning count 1 under the the edges of two clocks. Your need to assign it under 1 clock edge only.

To get a hint of what is a synthesizable code supported by your tool. You should find a synthesis manual that has templates for code blocks and their hardware counterparts.

Your design is like making a memory four count 1 with two clocks.

--
Amr Ali

 

[toki_rnm]

Re: Correct the errors .

ya signal is used as enable

 

[amraldo]

Re: Correct the errors .

You need to check your synthesizer document how a FF with Enable is coded.
ya that is enable should not be checked using an edge. It should be checked as a level.
If you need to check it as an edge, you will need to and the clock and the ya single in an and gate then use it as the clock to count1.
--
Amr

 

[kvingle]

Re: Correct the errors .

As said in previous post plz refer to synthesizer docs...
I see that you are using xilinx ISE. It has well written language templates available for ready reference in edit menu.

 

[bapodradhairyab]

Correct the errors .

you should not use a variable in two blocks that executes in parallel

first forget the software language when you start coding in HDL as syntax might be right but it will unusable code as it will be not implementable...

so think hardware
see available templets
try to think how your code can reach on digital circuit.
and than code some simplest codes like in steps adder , 4-bit adder, flipflops, counter, ...
and then start complex designs....

hope you got how to go with tools and HDLs