Hi,
I had the same problem with my last chip, TSMC 90nm. I had 100+ "Label shorts" when my LVS was run... It does say that schematic and layout match, so I said to myself, that is all LVS is used for and tapedout.... My chip does function completely, so I would say its a cadence bug. Unless someone else can correct me here on "label shorts".... I would say that are meaningless..... If you are DRC and LVS clean (it says schematic and layout match) you should be fine.
Jgk