dpaul
Advanced Member level 5
Would like suggestions on what & where I am going wrong.
Target: Develop a Hello World C code to be run on a MicroBlaze MCS processor implemented on Artix AC701 using Vivado 2014.4 and SDK.
What is done: Upto bit file generation of my top level design file which just contains the instantiation of the uB MCS.
I have performed the 'Generate Block Design' for my top level too.
Now before starting to use SDK, the two most imp. steps involved are
1. Importing the Hardware Platform Specification, and
2. Board support package
Problem:
From Vivado, when I do File > Export > Export Hardware, with the option "Include Bitstream", I get the error message that my "hardware handoff file (.sysdef)" is missing. Please the attached screen shot of my error message.
If I don't attach the bitstream, I still have the same problem.
write_hwdef -force -file D:/work/scratch/mb_mcs_core/mb_mcs_top.hdf
INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
I also tried the TCL commands.
When I run the 'write_hwdef' command I get the error message that -
write_hwdef -force -file ./mb_mcs_core.runs/synth_1/mb_mcs_core.hwdef
INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
I would like to know what has to be done to solve the above problem.
I have also opened a Xilinx community thread on this topic:
http://forums.xilinx.com/t5/Embedde...ackage-SDK-does-not-work-a-failed/td-p/677675
Target: Develop a Hello World C code to be run on a MicroBlaze MCS processor implemented on Artix AC701 using Vivado 2014.4 and SDK.
What is done: Upto bit file generation of my top level design file which just contains the instantiation of the uB MCS.
Code:
module mb_mcs_top(
input clk_top,
input reset_top,
output UART_Tx,
input UART_Rx
);
wire clk, reset;
wire uart_tx, uart_rx;
assign clk = clk_top;
assign reset = reset_top;
assign uart_rx = UART_Rx;
assign UART_Tx = uart_tx;
microblaze_mcs_0 microblaze_mcs_0_inst (
.Clk(clk), // input wire Clk
.Reset(reset), // input wire Reset
.UART_Rx(uart_rx), // input wire UART_Rx
.UART_Tx(uart_tx) // output wire UART_Tx
);
endmodule
I have performed the 'Generate Block Design' for my top level too.
Now before starting to use SDK, the two most imp. steps involved are
1. Importing the Hardware Platform Specification, and
2. Board support package
Problem:
From Vivado, when I do File > Export > Export Hardware, with the option "Include Bitstream", I get the error message that my "hardware handoff file (.sysdef)" is missing. Please the attached screen shot of my error message.
If I don't attach the bitstream, I still have the same problem.
write_hwdef -force -file D:/work/scratch/mb_mcs_core/mb_mcs_top.hdf
INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
I also tried the TCL commands.
Code:
set PROJECT_NAME "my_project"
set TOPLEVEL_NAME "toplevel"
write_hwdef -force -file ./$PROJECT_NAME.runs/synth_1/$TOPLEVEL_NAME.hwdef
write_sysdef -force -hwdef ./$PROJECT_NAME.runs/synth_1/$TOPLEVEL_NAME.hwdef -bitfile ./$PROJECT_NAME.runs/impl_1/$TOPLEVEL_NAME.bit -file ./$PROJECT_NAME.runs/impl_1/$TOPLEVEL_NAME.sysdef
When I run the 'write_hwdef' command I get the error message that -
write_hwdef -force -file ./mb_mcs_core.runs/synth_1/mb_mcs_core.hwdef
INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
I would like to know what has to be done to solve the above problem.
I have also opened a Xilinx community thread on this topic:
http://forums.xilinx.com/t5/Embedde...ackage-SDK-does-not-work-a-failed/td-p/677675
Last edited: