Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The synthesizer doesn't support "wait for" because today's FPGAs and CPLDs don't contain hardware for implementing an arbitrary time delay. Instead, you can build a digital timer using sequential logic such as a counter.
You can use "wait for" in your simulation test bench.
Some times when I creat new VHDL module, ISE don't ask me if it is for simulation or implementation, in source tab I don't find the module, and in the process tab I don't find the synthesis functions and others why?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
