The synthesizer doesn't support "wait for" because today's FPGAs and CPLDs don't contain hardware for implementing an arbitrary time delay. Instead, you can build a digital timer using sequential logic such as a counter.
You can use "wait for" in your simulation test bench.
Some times when I creat new VHDL module, ISE don't ask me if it is for simulation or implementation, in source tab I don't find the module, and in the process tab I don't find the synthesis functions and others why?