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[SOLVED] ERROR when simulating with extracted view

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AMSA84

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Hi guys,

When I do a simulation with the extracted view I get this error:

error: multiple case sensitive symbols have been created which match the case insensitive symbol 'C2'.

Does anyone know what this means? How can I solve this?

Regards.
 

erikl

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Seems you have (cell) symbols C2 as well as c2 (or C2xyz and c2xyz , where xyz means an arbitrary character string). This is permitted in schematics, but not for simulation, and, possibly, other tools like DRC, LVS ...

Such cell symbols cannot be differentiated.
 

timof

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Also, in the layout, different cells can have names that differ only by letter case.
 

AMSA84

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But how this is possible to happening if I don't have any other component in the circuit with C2 or c2? The only C2 component that I have in the schematic is a MOM capacitor.

This errors appears only when I am simulating with the extracted view. When doing the simulation without extracted view, everything goes normal.

I am confused. What's the solution?

timof, what you mean is that by any chance in the layout there are cell with the same name?
 

erikl

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Also, in the layout, different cells can have names that differ only by letter case.
Right, but it seems the LVS comparison tool doesn't like it.

This errors appears only when I am simulating with the extracted view.
When doing the simulation without extracted view, everything goes normal.

Maybe the parasitic elements extracted from layout receive names starting with the same characters (C2... , c2...), and the LVS cannot differentiate between their upper and lower case. Check the extracted netlist!
 

timof

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Right, but it seems the LVS comparison tool doesn't like it.

Well, I don't know - I see cells in GDS files different by only letter case all the time - so, I guess LVS is fine with that (I think there should be some switch/option in LVS that controls handling of such situations)

Maybe the parasitic elements extracted from layout receive names starting with the same characters (C2... , c2...), and the LVS cannot differentiate between their upper and lower case. Check the extracted netlist!

I think this is close.
If only first letters are the same (different case), but the following letters are different - this should not be a problem.

My guess is this - very often, parasitic tools give names to parasitic extracted elements as C1, C2, ... (R1, R2,... for resistors) - so, if you give the same name to intended capacitors - this is a conflict - as circuit simulation tools do not distinguish the letter case of elements (at least the basic SPICE), and do not allow different elements with the same name...

Try to generate plain text netlist (like DSPF file), and look for the names of parasitic capacitance elements, see if any of them have the same name as your intended capacitor (ignoring the letter case).

Max
 

AMSA84

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I guys, I have solved this issue. I just had to rename the capacitor instance.

Regards.
 

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