Error when doing QAM on ISE

[mmoctar]

This the code that i try to simulate but I have a error message, I try to do a qam for, an input 4 bits where the first is for in_phase and the second tthe quadrature.
thanx
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity qam is
Port ( clk : in STD_LOGIC;
Input : in STD_LOGIC_VECTOR (0 downto 3);
I_out : out INTEGER;
Q_out : out INTEGER);
end qam;

architecture Behavioral of qam is
begin
process
begin
wait until (clk'event and clk='1');
case ("Input(0)Input(1)") is
when "00" => I_out <= 1;
when "01" => I_out <= 2;
when "10" => I_out <= 3;
when "11" => I_out <= 4;
end case;
end process;
end Behavioral;


Started : "Check Syntax for qam".

=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Xilinx/ISEexamples/moc/qam.vhd" in Library work.
WARNING:HDLParsers:3350 - "C:/Xilinx/ISEexamples/moc/qam.vhd" Line 31. Null range: 0 downto 3
Entity <qam> compiled.
FATAL_ERROR:HDLParsers:vhpcstr.c:2033:$Id: vhpcstr.c,v 1.57.30.1 2006/08/16 15:27:36 sandeepd Exp $:200 - INTERNAL ERROR... while parsing "C:/Xilinx/ISEexamples/moc/qam.vhd" line 46. Contact your hot line. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com

Process "Check Syntax" failed

 

[fm_com_28]

Re: qam on ise

I think the two libraries ARITH and UNSIGNED don't work together in Xilinx, delete one of them.[/quote]

 

[qurthobi]

Re: qam on ise

maybe thats not

Input : in std_logic_vector (0 downto 3);

but

Input : in std_logic_vector (3 downto 0);

or

Input : in std_logic_vector (0 to 3);