counter:process(clk, reset) --process(sensitivity list)
begin
if reset'event and (reset = '1') then
s <= (others => '0');
elsif clk'event and (clk='1') then
count <= s;
end if;
end process;
counter:process(clk, reset) --process(sensitivity list)
begin
if (reset = '1') then
count <= (others => '0');
elsif clk'event and (clk='1') then
count <= s;
end if;
end process;
how are you driving the inputs to counter4 when simulating?
---------- Post added at 08:57 ---------- Previous post was at 08:56 ----------
Also, there are nothing driving ain or bin. You cannot add when there is nothing to add.
my current 4bit counter.
u1:ha port map(a => ain(3), b => bin(3), sum => s(3), c_out => c3);
u2:fa port map(a => ain(2), b => bin(2), sum => s(2), cin => c3, c_out => c2);
u3:fa port map(a => ain(1), b => bin(1), sum => s(1), cin => c2, c_out => c1);
u4:fa port map(a => ain(0), b => bin(0), sum => s(0), cin => c1, c_out => c);
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