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[SOLVED] ERROR when compiling.

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karthiga05

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When i compiled my counter, i received an error : "near ":": expecting : IN"
Can someone tell me what error is this?
thanks!
 

karthiga05

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this is my code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter4 is
port(count:eek:ut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);
end counter4;

architecture behav_counter4 of counter4 is

component ha port (a: in std_logic;
b: in std_logic;
sum: out std_logic;
c_out: out std_logic);
end component;

component fa port (a, b, cin : in std_logic;
sum, c_out : out std_logic);
end component;

signal cout:std_logic;
signal ain,bin,c,s:std_logic_vector(3 downto 0);

begin
--configuration specification
for ha1:ha use entity work.ha(rtl);
for fa1,fa2,fa3:fa use entity work.fa(fa_behav);

ha1:ha port map(a => ain(0), b => bin(0), sum => s(0), c_out => c(0));
fa1:ha port map(a => ain(1), b => bin(1), sum => s(1), cin => c(0), c_out => c(1));
fa2:ha port map(a => ain(2), b => bin(2), sum => s(2), cin => c(1), c_out => c(2));
fa3:ha port map(a => ain(3), b => bin(3), sum => s(3), cin => c(2), c_out => c(3));

begin
counter:process(clk, reset) --process(sensitivity list)
if reset'event and (reset = '1') then
s <= (others => '0');

elsif clk'event and (clk='1') then
count <= s;

end if;
end process;

end behav_counter;

---------- Post added at 13:29 ---------- Previous post was at 13:26 ----------

the error is at line 28.

---------- Post added at 13:43 ---------- Previous post was at 13:29 ----------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter4 is
port(count:eek:ut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);
end counter4;

architecture behav_counter4 of counter4 is

component ha port (a: in std_logic;
b: in std_logic;
sum: out std_logic;
c_out: out std_logic);
end component;

component fa port (a, b, cin : in std_logic;
sum, c_out : out std_logic);
end component;

signal cout:std_logic;
signal ain,bin,c,s:std_logic_vector(3 downto 0);

begin
--configuration specification
for u1:ha use entity work.ha(rtl);
for u2,u3,u4:fa use entity work.fa(fa_behav);

u1:ha port map(a => ain(0), b => bin(0), sum => s(0), c_out => c(0));
u2:fa port map(a => ain(1), b => bin(1), sum => s(1), cin => c(0), c_out => c(1));
u3:fa port map(a => ain(2), b => bin(2), sum => s(2), cin => c(1), c_out => c(2));
u4:fa port map(a => ain(3), b => bin(3), sum => s(3), cin => c(2), c_out => c(3));

begin
counter:process(clk, reset) --process(sensitivity list)
if reset'event and (reset = '1') then
s <= (others => '0');

elsif clk'event and (clk='1') then
count <= s;

end if;
end process;

end behav_counter;


THIS is the correct one! sry.
 

sanju_

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hi..
as i said in your pervious post put

"for u1:ha use entity work.ha(rtl);
for u2,u3,u4:fa use entity work.fa(fa_behav);
" ---------------------------------->
replace it to
"for all:ha use entity work.ha(rtl);
for all:fa use entity work.fa(fa_behav);" --->and put this two line of code above begin (place below singal declared)

and remove begin before process statement and put it after process


"begin
counter:process(clk, reset) --process(sensitivity list)
if reset'event and (reset = '1') then
s <= (others => '0'); "---->replace to


counter:process(clk, reset) --process(sensitivity list)
begin
if reset'event and (reset = '1') then
s <= (others => '0');



try this below code and tell weather you are getting same error as mentioned above that ("near ":": expecting : IN")?


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter4 is
port(count:eek:ut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);
end counter4;

architecture behav_counter4 of counter4 is

component ha port (a: in std_logic;
b: in std_logic;
sum: out std_logic;
c_out: out std_logic);
end component;

component fa port (a, b, cin : in std_logic;
sum, c_out : out std_logic);
end component;

signal cout:std_logic;
signal ain,bin,c,s:std_logic_vector(3 downto 0);
for all:ha use entity work.ha(rtl);
for all:fa use entity work.fa(fa_behav);
begin
--configuration specification


ha1:ha port map(a => ain(0), b => bin(0), sum => s(0), c_out => c(0));
fa1:fa port map(a => ain(1), b => bin(1), sum => s(1), cin => c(0), c_out => c(1));
fa2:fa port map(a => ain(2), b => bin(2), sum => s(2), cin => c(1), c_out => c(2));
fa3:fa port map(a => ain(3), b => bin(3), sum => s(3), cin => c(2), c_out => c(3));

--begin
counter:process(clk, reset)
begin --process(sensitivity list)
if (reset = '1') then
s <= (others => '0');

elsif clk'event and (clk='1') then
count <= s;

end if;
end process counter;
end behav_counter4;
 
Last edited:

karthiga05

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there are no more errors now. but my waveform shows uninitialized for my count(output)

here's my testbench:

library ieee;
use ieee.std_logic_1164.all;

entity mycounter_testbench4 is
end mycounter_testbench4;

architecture mycounter_tb4 of mycounter_testbench4 is

signal count: std_logic_vector(3 downto 0);
signal clk: std_logic:='0';
signal reset: std_logic;

component counter4
port(count:eek:ut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);

end component;

begin
counter_circuit : counter4
port map(count => count, clk => clk, reset => reset);

clock:process
begin
wait for 10ns;
clk <= not clk;
end process clock;

test_reset:process
begin
wait for 5ns; reset <= '1';
wait for 4ns; reset <= '0';
wait;
end process test_reset;

end mycounter_tb4;
 

sanju_

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that is due to their is no values for your...
"signal ain,bin,c"

your full adder and half adder is depending on ain,bin,c...their is no initial values assigned to this ain,bin and c.

and also i am not surely understood your logic i just cleared error's(syntax).
 

karthiga05

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my current 4bit counter.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter4 is
port(count:eek:ut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);
end counter4;

architecture behav_counter4 of counter4 is

component ha port (a: in std_logic;
b: in std_logic;
sum: out std_logic;
c_out: out std_logic);
end component;

component fa port (a, b, cin : in std_logic;
sum, c_out : out std_logic);
end component;

signal c,c1,c2,c3:std_logic;
signal ain,bin,s:std_logic_vector(3 downto 0);

--configuration specification
for all:ha use entity work.ha(rtl);
for all:fa use entity work.fa(fa_behav);

begin

u1:ha port map(a => ain(3), b => bin(3), sum => s(3), c_out => c3);
u2:fa port map(a => ain(2), b => bin(2), sum => s(2), cin => c3, c_out => c2);
u3:fa port map(a => ain(1), b => bin(1), sum => s(1), cin => c2, c_out => c1);
u4:fa port map(a => ain(0), b => bin(0), sum => s(0), cin => c1, c_out => c);

counter:process(clk, reset) --process(sensitivity list)
begin
if reset'event and (reset = '1') then
s <= (others => '0');

elsif clk'event and (clk='1') then
count <= s;

end if;
end process;

end behav_counter4;

---------- Post added at 14:29 ---------- Previous post was at 14:27 ----------

i set it to "0000" and now it shows "0000" only.
 

sanju_

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hi
as i said i didnt understand logic. what you did just i made syntax correction
if you look at the flow of your code line
if reset'event and (reset = '1') then ------> this will reset the code to 0000 at all rising edge
that means you are getting "0000" in positive level of reset code and "UUUU" in negative level of reset..
 

TrickyDicky

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first of all, your process is wrong:

Code:
counter:process(clk, reset) --process(sensitivity list)
begin
if reset'event and (reset = '1') then
s <= (others => '0');

elsif clk'event and (clk='1') then
count <= s;

end if;
end process;

You cannot do this. You are reading reset and clock as if they were both clocks. FPGAs will only allow 1 clock per register.
Secondly, S is the output of the adders, so you cannot reset it in this process. You need to reset count, not S.

here is the replacement:

Code:
counter:process(clk, reset) --process(sensitivity list)
begin
if (reset = '1') then
count <= (others => '0');

elsif clk'event and (clk='1') then
count <= s;

end if;
end process;
 

karthiga05

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i;ve changed according to what youve asked me to but it still shows the same error.
 

TrickyDicky

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how are you driving the inputs to counter4 when simulating?

---------- Post added at 08:57 ---------- Previous post was at 08:56 ----------

Also, there are nothing driving ain or bin. You cannot add when there is nothing to add.
 

karthiga05

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter4 is
port(count:eek:ut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);
end counter4;

architecture behav_counter4 of counter4 is

component ha port (a: in std_logic;
b: in std_logic;
sum: out std_logic;
c_out: out std_logic);
end component;

component fa port (a, b, cin : in std_logic;
sum, c_out : out std_logic);
end component;

signal c,c1,c2,c3:std_logic;
signal ain,bin,s:std_logic_vector(3 downto 0);

--configuration specification
for all:ha use entity work.ha(rtl);
for all:fa use entity work.fa(fa_behav);

begin

u1:ha port map(a => ain(3), b => bin(3), sum => s(3), c_out => c3);
u2:fa port map(a => ain(2), b => bin(2), sum => s(2), cin => c3, c_out => c2);
u3:fa port map(a => ain(1), b => bin(1), sum => s(1), cin => c2, c_out => c1);
u4:fa port map(a => ain(0), b => bin(0), sum => s(0), cin => c1, c_out => c);

counter:process(clk, reset) --process(sensitivity list)
begin
if reset'event and (reset = '1') then
s <= (others => '0');

elsif clk'event and (clk='1') then
count <= s;

end if;
end process;

count <= s;

end behav_counter4;


testbench::

library ieee;
use ieee.std_logic_1164.all;

entity mycounter_testbench4 is
end mycounter_testbench4;

architecture mycounter_tb4 of mycounter_testbench4 is

signal count: std_logic_vector(3 downto 0);
signal clk: std_logic:='0';
signal reset: std_logic;

component counter4
port(count:eek:ut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);

end component;

begin
counter_circuit : counter4
port map(count => count, clk => clk, reset => reset);

clock:process
begin
wait for 10ns;
clk <= not clk;
end process clock;

test_reset:process
begin
wait for 5ns; reset <= '1';
wait for 4ns; reset <= '0';
wait;
end process test_reset;

end mycounter_tb4;

---------- Post added at 16:26 ---------- Previous post was at 16:25 ----------

how are you driving the inputs to counter4 when simulating?

---------- Post added at 08:57 ---------- Previous post was at 08:56 ----------

Also, there are nothing driving ain or bin. You cannot add when there is nothing to add.

--configuration specification
for all:ha use entity work.ha(rtl);
for all:fa use entity work.fa(fa_behav);


isnt this suppose to be extracting the architecture part of fulladder and halfadder?
 

TrickyDicky

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yes, but you need to give them an input, external to the counter4 entity.
 

karthiga05

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i assigned "0000" to the signals already. now it shows "0000" all the way in the waveform.
 

TrickyDicky

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if you assing "0000" to all ain and bin, then the output is going to be 0000
You need to change ain and bin over time, to give you different sum results.
 

karthiga05

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but i thought tht is already done in the configuration part?
 

sanju_

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my current 4bit counter.


u1:ha port map(a => ain(3), b => bin(3), sum => s(3), c_out => c3);
u2:fa port map(a => ain(2), b => bin(2), sum => s(2), cin => c3, c_out => c2);
u3:fa port map(a => ain(1), b => bin(1), sum => s(1), cin => c2, c_out => c1);
u4:fa port map(a => ain(0), b => bin(0), sum => s(0), cin => c1, c_out => c);

this part is doing only half adder and full adder of respective inputs
and you are trying to put final output of this above code to your count at clk edge
so you need to think the logic such that ain,bin and c values should give output 0001,0010,0011 so..on...



are you trying this code logic here also??
https://www.edaboard.com/threads/216613/
https://www.edaboard.com/threads/216818/
 

TrickyDicky

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the configuration just tells the compiler which architecture to use for your components. If you have only have one architecture, then the configurations are useless.
 

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