[SOLVED] Error- "Unknown or bad value for genvar" msg in a Xilinx IP

[dpaul]

I cannot figure out why VCS is throwing this error. Given below is the error message and then part of the code where error occurs.

VCS error message:
Error-[V2KGEUV] Unknown or bad value for genvar
/home/dpaul/rev28462_fpga/src/top_modules/axi_interconnect_v1_06_a/ict106_protocol_conv_bank.v, 228
Elaboration time unknown or bad value encountered for generate if-statement
condition expression.
Please make sure it is elaboration time constant.

module ict106_protocol_conv_bank #
  (
  // parameter declarations come here (OVERRIDDEN by top-level parameters)
   )
  (
   // AXI signals come here
   );

  // some wire declarations

genvar slot;

generate
for (slot=0;slot<C_NUM_SLOTS;slot=slot+1) begin : gen_protocol_slot
if ((C_AXI_PROTOCOL[slot*32+:32] == P_AXILITE) || (C_AXI_PROTOCOL[slot*32+:32] == P_AXI3)) begin : gen_prot_conv
ict106_axi_protocol_converter #(
// some AXI parameters come here
) conv_inst (
// AXI port connections come here
);
// Bunch of assign statements
end
end
endgenerate

endmodule

Line 228 is:
if ((C_AXI_PROTOCOL[slot*32+:32] == P_AXILITE) || (C_AXI_PROTOCOL[slot*32+:32] == P_AXI3)) begin : gen_prot_conv

Now I give the parameter values which are SUPPOSED TO BE TAKEN during compilation:
C_NUM_SLOTS = 2
C_AXI_PROTOCOL = {1{32'h00000002}}
P_AXI3 = 32'h1;
P_AXILITE = 32'h2;

I have even manually substituted some of the parameters by their values, but the result is the same. Any hints as to how do I debug this or what is causing the error?

Note- This code snippet where the error is occuring is part of the Xilinx AXI4 Interconnect IP. I am integrating this IP in my system and so have only changed the parameters in the top-level file of the AXI interconnect.

 

[dpaul]

The problem was entirely due to wrong parameter values being passed down from the top-level.