i also get a critical warning: CRITICAL WARNING: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port c0_sys_clk_n is Single-Ended but has an IOStandard of DIFF_SSTL15 which can only support Differential
I'm thinking this may be the error & i should change io standard but this constraint was generated by xilinx,so should i do it/not ?
IBUFGDS is not like other logic elements, which can be connected freely. The inputs are connected directly to physical pins, so you must use pins that have an IBUFGDS.
This might be an issue with IP integrator or using a hierarchical design. I recall seeing some issues like this in the past, but I don't think I worked directly on it until it was time to just get things done. A year ago, some of the Xilinx cores were not ready for ip-integrator and we would routinely use the HDL source and modify the clocking scheme to match our FPGA (which would have been overmapped on MMCMs, PLLs, and BUFGs).
In this case, it is possible something uses the pad as a clock in the fpga top level. This would infer the BUFG from that pin. When the pre-synthesized MIG netlist was merged with the top level, the input to the ibufgds now appears to come from a bufg.
There is probably an answer record for this problem somewhere.
In this case, it is possible something uses the pad as a clock in the fpga top level. This would infer the BUFG from that pin. When the pre-synthesized MIG netlist was merged with the top level, the input to the ibufgds now appears to come from a bufg.
My design uses MIG ip core for DDR3.The example project that xilinx gives along with ip core got implemented succesfully.The only change i did in his example_top given by xilinx was to add my user_logic(fsm) & some fifo's & a adc interface & comment out his traffic generator.
The signals c0_sys_clk_p & n are input to my top module.I did not insert any IBUFG in its path.The signal flow in entire path comes down to code in #1.
There are 2-3 modules with just port mapping clk signal & finally modules shown in #1.
Attached is the implementation log file(Log_file.txt) & XDC file provided by xilinx which i'm using(uploaded as mig_7series_0.txt).
There are warnings about the c0_sys_clk pin and their placement and that the tools don't think it's connected to the correct pin or connected to the top level.
You also have warnings of invalid attributes being used.
After synthesizing my design, i opened the schematic of my design.
I see that my input c0_sys_clk_p is connected to IBUFG, the output of which is connected to BUFG which is getting connected to IBUFDS in i/p core.(which is what the tool's complaining about)
I noticed that this additional IBUFG & BUFG are coming onto signal path because i was giving c0_sys_clk_p (input) to ip_core & two other modules(fifo & fsm module) for which i want to have the same clock.
How can i do this ?To have same clock for ip_core & those two other modules. One method is give c0_sys_clk_p only to ip_core & have another input clock which has same period as c0_sys_clk_p which drives those other modules.
Is there any other way,which does not involve incorporating an additional clock input onto my top module ?