rahdirs
Advanced Member level 1

ERROR: [Drc 23-20] Rule violation (REQP-61)
While i was implementing my project,i'm getting a DRC error.
Full error(could not post in title bcoz of length constraint).
ERROR: [Drc 23-20] Rule violation (REQP-61) ibufds_connects_I_active - IBUFDS /.../.u_ibufg_sys_clk pin I has an invalid driver c0_sys_clk_p_BUFG_inst
The signal that he mentions c0_sys_clk_p is an i/p to my top module.Invalid driver ?How do i drive my i/p ?
Digging down into his ip core my input clock goes into:
and in mig_7series_v2_3_clk_ibuf
- - - Updated - - -
Looking into my UCF file,
i also get a critical warning: CRITICAL WARNING: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port c0_sys_clk_n is Single-Ended but has an IOStandard of DIFF_SSTL15 which can only support Differential
I'm thinking this may be the error & i should change io standard but this constraint was generated by xilinx,so should i do it/not ?
While i was implementing my project,i'm getting a DRC error.
Full error(could not post in title bcoz of length constraint).
ERROR: [Drc 23-20] Rule violation (REQP-61) ibufds_connects_I_active - IBUFDS /.../.u_ibufg_sys_clk pin I has an invalid driver c0_sys_clk_p_BUFG_inst
The signal that he mentions c0_sys_clk_p is an i/p to my top module.Invalid driver ?How do i drive my i/p ?
Digging down into his ip core my input clock goes into:
Code:
c0_u_ddr3_clk_ibuf : mig_7series_v2_3_clk_ibuf
generic map
(
SYSCLK_TYPE => SYSCLK_TYPE,
DIFF_TERM_SYSCLK => C0_DIFF_TERM_SYSCLK
)
port map
(
sys_clk_p => c0_sys_clk_p,
sys_clk_n => c0_sys_clk_n,
sys_clk_i => c0_sys_clk_i,
mmcm_clk => c0_mmcm_clk
);
Code:
IBUFGDS #
(
.DIFF_TERM (DIFF_TERM_SYSCLK),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
- - - Updated - - -
Looking into my UCF file,
# PadFunction: IO_L13P_T2_MRCC_38
set_property VCCAUX_IO DONTCARE [get_ports {c0_sys_clk_p}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {c0_sys_clk_p}]
set_property PACKAGE_PIN E16 [get_ports {c0_sys_clk_p}]
# PadFunction: IO_L13N_T2_MRCC_38
set_property VCCAUX_IO DONTCARE [get_ports {c0_sys_clk_n}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {c0_sys_clk_n}]
set_property PACKAGE_PIN D16 [get_ports {c0_sys_clk_n}]
i also get a critical warning: CRITICAL WARNING: [Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port c0_sys_clk_n is Single-Ended but has an IOStandard of DIFF_SSTL15 which can only support Differential
I'm thinking this may be the error & i should change io standard but this constraint was generated by xilinx,so should i do it/not ?
Last edited: