tri2061990
Newbie level 5
My code
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity bai2 is
port( din :in std_logic_vector(2 downto 0);
dout
ut std_logic_vector(7 downto 0);
control:in std_logic );
end bai2;
architecture a of bai2 is
begin
giai_ma: process(control,din)
begin
if control ='1' then
case Din is
when "000"=> dout<="11111110";
when "001"=> dout<="11111101";
when "010"=> dout<="11111011";
when "011"=> dout<="11110111";
when "100"=> dout<="11101111";
when "101"=> dout<="11011111";
when "110"=> dout<="10111111";
when "111"=> dout<="01111111";
when others=>dout<="00000000";
end case;
end if;
end process giai_ma;
end a;
My error
# vsim b2
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: Failed to find design unit work.b2.
# Optimization failed
# Error loading design
Help me ,please
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity bai2 is
port( din :in std_logic_vector(2 downto 0);
dout
ut std_logic_vector(7 downto 0);control:in std_logic );
end bai2;
architecture a of bai2 is
begin
giai_ma: process(control,din)
begin
if control ='1' then
case Din is
when "000"=> dout<="11111110";
when "001"=> dout<="11111101";
when "010"=> dout<="11111011";
when "011"=> dout<="11110111";
when "100"=> dout<="11101111";
when "101"=> dout<="11011111";
when "110"=> dout<="10111111";
when "111"=> dout<="01111111";
when others=>dout<="00000000";
end case;
end if;
end process giai_ma;
end a;
My error
# vsim b2
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: Failed to find design unit work.b2.
# Optimization failed
# Error loading design
Help me ,please