Error on counting distance between 2 rising edges

I'm trying to count distance between two rising edges. i found a problem when i install the program into my Xilinx Spartan 3 starter kit, which the output is different from what i expected. The process is simply:

process(clock, clk_div)
begin

if ( (clock'event) and (clock = '1') ) then

temp <= temp + "000000000000000000000001"; --keep track the distance

if (clk_div = '0') then -- '0' because clk_div '1' length is as 1 clock wave

velocity <= temp; --save it to a register

temp <= "000000000000000000000000"; --reset the count


end if;

Click to expand...

clk_div is an enable signal and sync with the clk. The simulation result using ISE 9.2i was perfect but the result when the whole program is installed is not as what i expected. After i check for errors, i found out that the temp signal is not incrementing. The value of signal temp is incrementing only once for any kind of inputs (so the velocity is always 1)

Does anybody know how can the error occur and how to fix it??

So far, i can only think that there's delay inside the FPGA which messed up the counting. Is it possible?? Will it help if i build a state machine for the signals??

sorry if my english and explanation is catastrophic.. THX!!!

Cheers,
Brian Angg

i just tried to make a dummy signal to replace clk_div, and the program works.. :/