Error Message With VHDL CODE

[venkatpasumarthi]

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
entity comp is
port(a : in std_logic_vector(7 downto 0);
      y : out std_logic_vector(7 downto 0));
end comp;
architecture dataflow of comp is
  signal temp: std_logic;
begin
 
y<=  not(a) + "00000001"; 
 
end dataflow;

---

and it is showing the error

** Error: D:/modelsim_projects/2scmpliment.vhd(13): No feasible entries for infix operator "+".

 

[FvM]

std_logic_vector isn't a numeric data type. No arithmetic operations defined for it. You can use unsigned type instead Or use the non-IEEE library std_arithmetic_unsigned. Or apply type casts like

y<=  std_logic_vector(unsigned(not(a)) + unsigned("00000001"));