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ERROR:MapLib:87 - There are invalid FMAPs in the design

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umairsiddiqui

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i am currently debugging the cpu code, and try for first rough fpga
implementation (spartan3 starter kit). in cpu for a short cut,
i used a xilinx macro "adsu16".

i'm using Xilinx Project Navigator 6.1.03i. the design
properly synthsize, translate but fail on mapping
and shows following error and warnings.

please help with issue.

also i would be nice if any one of you write the code of adsu16 in
vhdl or verilog??? ;-)

Code:
Release 6.1.03i Map G.26
Xilinx Mapping Report File for Design 'top'

Design Information
------------------
Command Line   : D:/installed-software/Xilinx/bin/nt/map.exe -intstyle ise -p
xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o top_map.ncd top.ngd
top.pcf 
Target Device  : x3s200
Target Package : ft256
Target Speed   : -4
Mapper Version : spartan3 -- $Revision: 1.16 $
Mapped Date    : Tue Jan 31 02:27:29 2006

Design Summary
--------------
Number of errors   :   1
Number of warnings :  16

Section 1 - Errors
------------------
ERROR:MapLib:87 - There are invalid FMAPs in the design.  See warnings section
   in map report for details of FMAP problems.

Section 2 - Warnings
--------------------
WARNING:MapLib:541 - Internal signals in FMAP symbol
   "u1/datapath/u2/u1/u1/XLXI_1/I_36_291" (output
   signal=u1/datapath/u2/u1/u1/XLXI_1/I5) drive logic outside the MAP:
   	u1/datapath/u2/u1/u1/XLXI_1/SUB15
WARNING:MapLib:541 - Internal signals in FMAP symbol
   "u1/datapath/u2/u1/u1/XLXI_1/I_36_287" (output
   signal=u1/datapath/u2/u1/u1/XLXI_1/I4) drive logic outside the MAP:
   	u1/datapath/u2/u1/u1/XLXI_1/SUB15
WARNING:MapLib:541 - Internal signals in FMAP symbol
   "u1/datapath/u2/u1/u1/XLXI_1/I_36_283" (output
   signal=u1/datapath/u2/u1/u1/XLXI_1/I3) drive logic outside the MAP:
   	u1/datapath/u2/u1/u1/XLXI_1/SUB15
WARNING:MapLib:541 - Internal signals in FMAP symbol
   "u1/datapath/u2/u1/u1/XLXI_1/I_36_279" (output
   signal=u1/datapath/u2/u1/u1/XLXI_1/I2) drive logic outside the MAP:
   	u1/datapath/u2/u1/u1/XLXI_1/SUB15
WARNING:MapLib:541 - Internal signals in FMAP symbol
   "u1/datapath/u2/u1/u1/XLXI_1/I_36_275" (output
   signal=u1/datapath/u2/u1/u1/XLXI_1/I0) drive logic outside the MAP:
   	u1/datapath/u2/u1/u1/XLXI_1/SUB15
WARNING:MapLib:541 - Internal signals in FMAP symbol
   "u1/datapath/u2/u1/u1/XLXI_1/I_36_272" (output
   signal=u1/datapath/u2/u1/u1/XLXI_1/I1) drive logic outside the MAP:
   	u1/datapath/u2/u1/u1/XLXI_1/SUB15
WARNING:MapLib:541 - Internal signals in FMAP symbol
   "u1/datapath/u2/u1/u1/XLXI_1/I_36_23" (output
   signal=u1/datapath/u2/u1/u1/XLXI_1/I15) drive logic outside the MAP:
   	u1/datapath/u2/u1/u1/XLXI_1/SUB15
WARNING:MapLib:541 - Internal signals in FMAP symbol
   "u1/datapath/u2/u1/u1/XLXI_1/I_36_22" (output
   signal=u1/datapath/u2/u1/u1/XLXI_1/I14) drive logic outside the MAP:
   	u1/datapath/u2/u1/u1/XLXI_1/SUB15
WARNING:MapLib:541 - Internal signals in FMAP symbol
   "u1/datapath/u2/u1/u1/XLXI_1/I_36_21" (output
   signal=u1/datapath/u2/u1/u1/XLXI_1/I13) drive logic outside the MAP:
   	u1/datapath/u2/u1/u1/XLXI_1/SUB15
WARNING:MapLib:541 - Internal signals in FMAP symbol
   "u1/datapath/u2/u1/u1/XLXI_1/I_36_20" (output
   signal=u1/datapath/u2/u1/u1/XLXI_1/I12) drive logic outside the MAP:
   	u1/datapath/u2/u1/u1/XLXI_1/SUB15
WARNING:MapLib:541 - Internal signals in FMAP symbol
   "u1/datapath/u2/u1/u1/XLXI_1/I_36_19" (output
   signal=u1/datapath/u2/u1/u1/XLXI_1/I11) drive logic outside the MAP:
   	u1/datapath/u2/u1/u1/XLXI_1/SUB15
WARNING:MapLib:541 - Internal signals in FMAP symbol
   "u1/datapath/u2/u1/u1/XLXI_1/I_36_18" (output
   signal=u1/datapath/u2/u1/u1/XLXI_1/I10) drive logic outside the MAP:
   	u1/datapath/u2/u1/u1/XLXI_1/SUB15
WARNING:MapLib:541 - Internal signals in FMAP symbol
   "u1/datapath/u2/u1/u1/XLXI_1/I_36_17" (output
   signal=u1/datapath/u2/u1/u1/XLXI_1/I9) drive logic outside the MAP:
   	u1/datapath/u2/u1/u1/XLXI_1/SUB15
WARNING:MapLib:541 - Internal signals in FMAP symbol
   "u1/datapath/u2/u1/u1/XLXI_1/I_36_16" (output
   signal=u1/datapath/u2/u1/u1/XLXI_1/I8) drive logic outside the MAP:
   	u1/datapath/u2/u1/u1/XLXI_1/SUB15
WARNING:MapLib:541 - Internal signals in FMAP symbol
   "u1/datapath/u2/u1/u1/XLXI_1/I_36_295" (output
   signal=u1/datapath/u2/u1/u1/XLXI_1/I6) drive logic outside the MAP:
   	u1/datapath/u2/u1/u1/XLXI_1/SUB15
WARNING:MapLib:541 - Internal signals in FMAP symbol
   "u1/datapath/u2/u1/u1/XLXI_1/I_36_299" (output
   signal=u1/datapath/u2/u1/u1/XLXI_1/I7) drive logic outside the MAP:
   	u1/datapath/u2/u1/u1/XLXI_1/SUB15

Section 3 - Informational
-------------------------
INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP)
INFO:MapLib:159 - Net Timing constraints on signal clk are pushed forward
   through input buffer.
 

echo47

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I don't have ISE 6.1.03i, so I tried 8.1.01i. It compiled and routed with no error messages.
 

umairsiddiqui

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well i've made few changes in cpu code which can noted in cpu.vhd, cpu_pkg.vhd, dp.vhd and con.vhd. just search
Code:
@new

i hope this might solve some problems...but synthesis tool now report that top.vhd now support (Minimum period: 21.976ns (Maximum Frequency: 45.503MHz).

so kindly provide help with spartan 3 dcm configuration...i tried with architecture wizard but generated component has too many ports...i am confuse with this issue.

please tell me how to use dcm in top.vhd and how connected the cpu and rest of logic with "clkdiv".

any way i'm attaching the files as well, the baud_timer.vhd need to be changed as it is for 50MHz and so as top.ucf.

atleast fix the top.vhd and top.ucf, incorporating dcm related changes
 

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