error in vhdl simulation

Status
Not open for further replies.
R

rado

Member level 2
Joined
Feb 15, 2014
Messages
42
Helped
1
Reputation
2
Reaction score
1
Trophy points
8
Activity points
293
Iam using ModelSim pe student edition to simulate vhdl code.
but shows an error as," Empty source files "
what to do ?
I only started using ModelSim, not well familiarized.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…