Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

error in vhdl simulation

Status
Not open for further replies.
R

rado

Member level 2
Member level 2
Joined
Feb 15, 2014
Messages
42
Helped
1
Reputation
2
Reaction score
1
Trophy points
8
Visit site
Activity points
293
Iam using ModelSim pe student edition to simulate vhdl code.
but shows an error as," Empty source files "
what to do ?
I only started using ModelSim, not well familiarized.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top