Error in VHDL assignments

[Binome]

Hi,
I have a strange error. Here is my code:

library ieee;
use     ieee.std_logic_1164.all;
use 	ieee.std_logic_arith.all;
use		ieee.math_real.all;

library work;
use		work.fft_pack.all;

entity fft_g is
	generic(
		Dwidth		: integer:=8;
		Twidth		: integer:=8;
		N			: integer:=8;
		log2N		: integer:=3;
		pipelined	: integer:=2;
		ifft		: boolean:=false);
	port(
		clk			: in  std_logic;
		rst			: in  std_logic;
		en			: in  std_logic;
		p_I			: in  fft_data(N-1 downto 0);
		p_Q			: in  fft_data(N-1 downto 0);
		x_I			: out fft_data(N-1 downto 0);
		x_Q			: out fft_data(N-1 downto 0);
		overflow	: out std_logic_vector(log2N-1 downto 0));
end fft_g;

architecture rtl of fft_g is
	signal in_ifft_I		: fft_data(N-1 downto 0);
	signal in_ifft_Q		: fft_data(N-1 downto 0);
	signal out_ifft_I		: fft_data(N-1 downto 0);
	signal out_ifft_Q		: fft_data(N-1 downto 0);
    
    signal sigtmp_I			: sig_tmp(log2N downto 0, N-1 downto 0);
    signal sigtmp_Q			: sig_tmp(log2N downto 0, N-1 downto 0);

begin

fft_x : if ifft=false generate
	pas_de_croisement : for k in 0 to N-1 generate
		in_ifft_I(k) <= p_I(k);
		in_ifft_Q(k) <= p_Q(k);
		x_I(k) <= out_ifft_I(k);
		x_Q(k) <= out_ifft_Q(k);
	end generate pas_de_croisement;
end generate fft_x;
	
init : for j in 0 to N-1 generate		
	sigtmp_I(0,j) <= in_ifft_I(j);
	sigtmp_Q(0,j) <= in_ifft_Q(j);
end generate init;
		
end rtl;

Modelsim shows me in_ifft_I and in_ifft_Q are correct but sigtmp_I and sigtmp_Q are X so the init loop should not be executed but I don't know why.
Could someone explain?
Thanks.

 

[ads-ee]

Hi,
I have a strange error.

Modelsim shows me in_ifft_I and in_ifft_Q are correct but sigtmp_I and sigtmp_Q are X so the init loop should not be executed but I don't know why.
Could someone explain?
Thanks.

I don't understand what you are seeing as an error. Is it that the init loop is getting executed giving you X? or are you complaining that it's not getting executed and you are getting X? Are you sure the sigtmp_I/Q aren't X because they got assigned a U from in_ifft_I/Q at time 0?

I was going to try running it but you have custom types, so I won't bother.

 

[Binome]

I don't understand what you are seeing as an error. Is it that the init loop is getting executed giving you X? or are you complaining that it's not getting executed and you are getting X? Are you sure the sigtmp_I/Q aren't X because they got assigned a U from in_ifft_I/Q at time 0?

I don't know that. How could I look at this?

I was going to try running it but you have custom types, so I won't bother.

Right, here are the types:

type fft_data is array(natural range <>) of std_logic_vector(7 downto 0);
type sig_tmp is array(natural range <>,natural range <>) of std_logic_vector(7 downto 0);

 

[TrickyDicky]

I don't know that. How could I look at this?

But running a simulation. Expand the busses. A bus that has values all 'U' will display the bus as 'X'

Right, here are the types:

type fft_data is array(natural range <>) of std_logic_vector(7 downto 0);
type sig_tmp is array(natural range <>,natural range <>) of std_logic_vector(7 downto 0);

Not really much use, as we dont have the testbench.

But the code that you posted is pretty usless if ifft=false as the outputs are unconnected.

 

[FvM]

Looks like a useless piece of HDL code. Most signals are either not read (in_ifft_xx) or not assigned (out_ifft_xx) and thus discarded in synthesis. The init block for sig_tmp_xx is only "executed" once, before meaningful values might be assigned to p_I and p_Q.

Everything normal operation. Come back with better considered code.

 

[Binome]

It's a very simplified part of the complete code. out_ifft_xx are assigned in another part, in_ifft_xx are used in a function.
I HAVE to use all these signals.
What I don't understand is why the sigtmp signals are not the same as the in_fft ones.

 

[TrickyDicky]

What I don't understand is why the sigtmp signals are not the same as the in_fft ones.

At what point in time?
At time zero the input will be assigned, but the other assigments take 1 delta per assignment. So sigtmp wont be assigned a value until 0ns + 2 deltas

- - - Updated - - -

What I don't understand is why the sigtmp signals are not the same as the in_fft ones.

At what point in time?
At time zero the input will be assigned, but the other assigments take 1 delta per assignment. So sigtmp wont be assigned a value until 0ns + 2 deltas

 

[Binome]

I look at the signals in Modelsim. How could I know the value at 0 then at one delta?

 

[TrickyDicky]

The main question is - why do you care? In a real system, they will just be wires.
Why not simulate the system normally and see the output values at the correct times?