Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 module imp(clk, addr, we_f, en_f, do_r, do_g, do_b, do_t1, do_t2); input clk; input en; input we; output [10:0]do_r[483:0]; output [10:0]do_g[483:0]; output [10:0]do_b[483:0]; output [10:0]do_t1[483:0]; output [10:0]do_t2[483:0]; reg [10:0]temp_r; reg [10:0]temp_g; reg [10:0]temp_b; reg [10:0]addr; reg [10:0]r1=10'b0000000001; reg [10:0]r2; reg decision; reg cn1; reg cn2; // prcedural loop for getting bins from ROM & processiing them always @(posedge clk) begin for (addr=0; addr<=484; addr=addr+1) rdrom gt1(clk, en_f, addr, temp_r); grom gt2(clk, en_f, addr, temp_g); brom gt3(clk, en_f, addr, temp_b); if (addr==0) begin ram_r gt4(clk, we_f, en_f, addr, temp_r, do_r); ram_g gt5(clk, we_f, en_f, addr, temp_g, do_g); ram_b gt6(clk, we_f, en_f, addr, temp_b, do_b ); ram_t1 gt7(clk, we_f, en_f, addr, r1, do_t1 ); ram_t2 gt8(clk, we_f, en_f, addr, r1, do_t2 ); break; end if(ram_r[addr]==0 && ram_g[addr]==0 && ram_b[addr]==0 ) begin r2<= addr; for(i=0; i<r2; i=i+1) begin segmtnbox gt9(temp_r, temp_g, temp_b, RAM_r[i], RAM_g[i], RAM_b[i], decision, w9s, w11dif, cin); if(decision==1) begin ram_t2 gt10(clk, we_f, en_f, addr, i, d_t2); RAM_t1[addr]=RAM_t1[addr]+1; break; end cn1=1; end if(cn1==1) begin ram_r gt11(clk, we_f, en_f, addr, temp_r, do_r); ram_g gt12(clk, we_f, en_f, addr, temp_g, do_g); ram_b gt13(clk, we_f, en_f, addr, temp_b, do_b); ram_t1 gt14(clk, we_f, en_f, addr, r1, do_t1 ); ram_t2 gt15(clk, we_f, en_f, addr, r1, do_t2 ); end end
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