Error in Verilog problem

[Gaurav Sarode]

Hello everyone I am implementing Image segmentation on FPGA, for that i have to compare the pixel values with each other. I have stored image pixel values in ROM, and now want to put them in RAM and simultaneously compare them with previous entries in RAM.I have written this code given bellow but getting lot of errors. So please help

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module imp(clk, addr, we_f, en_f, do_r, do_g, do_b, do_t1, do_t2);
 
input clk; input en; input we;
 
output [10:0]do_r[483:0]; 
output [10:0]do_g[483:0];
output [10:0]do_b[483:0];
output [10:0]do_t1[483:0];
output [10:0]do_t2[483:0];
 
reg [10:0]temp_r;
reg [10:0]temp_g;
reg [10:0]temp_b;
reg [10:0]addr;
reg [10:0]r1=10'b0000000001;
reg [10:0]r2;
reg decision;
reg cn1;
reg cn2;
 
// prcedural loop for getting bins from ROM & processiing them
 
always @(posedge clk)
 
begin
    for (addr=0; addr<=484; addr=addr+1)
    
    rdrom gt1(clk, en_f, addr, temp_r);
    grom gt2(clk, en_f, addr, temp_g);
    brom gt3(clk, en_f, addr, temp_b);
    
        if (addr==0)
        begin
        ram_r gt4(clk, we_f, en_f, addr, temp_r, do_r);
        ram_g gt5(clk, we_f, en_f, addr, temp_g, do_g);
        ram_b gt6(clk, we_f, en_f, addr, temp_b, do_b );
        ram_t1 gt7(clk, we_f, en_f, addr, r1, do_t1 );
        ram_t2 gt8(clk, we_f, en_f, addr, r1, do_t2 );
        break;
        end
    
        if(ram_r[addr]==0 && ram_g[addr]==0 && ram_b[addr]==0 )
    
        begin
        r2<= addr;
    
        for(i=0; i<r2; i=i+1)
        begin
        segmtnbox gt9(temp_r, temp_g, temp_b, RAM_r[i], RAM_g[i], RAM_b[i], decision, w9s, w11dif, cin);
    
            if(decision==1)
            begin
                ram_t2 gt10(clk, we_f, en_f, addr, i, d_t2);
                RAM_t1[addr]=RAM_t1[addr]+1;
        
                break;
                
            end
    
            cn1=1;
    
        end
        
        if(cn1==1)
        begin
        
            ram_r gt11(clk, we_f, en_f, addr, temp_r, do_r);
            ram_g gt12(clk, we_f, en_f, addr, temp_g, do_g);
            ram_b gt13(clk, we_f, en_f, addr, temp_b, do_b);
            ram_t1 gt14(clk, we_f, en_f, addr, r1, do_t1 );
            ram_t2 gt15(clk, we_f, en_f, addr, r1, do_t2 );
            
        end
    
    end

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[er.akhilkumar]

There is an error in input/output declaration. You have used "we" instead of "we_f" and "en" instead of "en_f". You have used internal bus "addr" which is of same name as the port name. We cannot use internal signals and ports with the same name.

 

[Gaurav Sarode]

@ Akhilkumar
Thanx for ur rpl

I have made changes that u suggested but still m getting errors, m using Quartus II

the errors are as follows
Error (10170): Verilog HDL syntax error at imp.v(28) near text "gt1"; expecting "<=", or "="
Error (10170): Verilog HDL syntax error at imp.v(29) near text "gt2"; expecting "<=", or "="
Error (10170): Verilog HDL syntax error at imp.v(30) near text "gt3"; expecting "<=", or "="
Error (10170): Verilog HDL syntax error at imp.v(34) near text "("; expecting ";", or ","
Error (10149): Verilog HDL Declaration error at imp.v(34): identifier "temp_r" is already declared in the present scope
Error (10170): Verilog HDL syntax error at imp.v(34) near text ")"; expecting ";", or ","
Error (10170): Verilog HDL syntax error at imp.v(35) near text "("; expecting ";", or ","
Error (10149): Verilog HDL Declaration error at imp.v(35): identifier "temp_g" is already declared in the present scope
Error (10170): Verilog HDL syntax error at imp.v(35) near text ")"; expecting ";", or ","
Error (10170): Verilog HDL syntax error at imp.v(36) near text "("; expecting ";", or ","
Error (10149): Verilog HDL Declaration error at imp.v(36): identifier "temp_b" is already declared in the present scope
Error (10170): Verilog HDL syntax error at imp.v(36) near text ")"; expecting ";", or ","
Error (10170): Verilog HDL syntax error at imp.v(37) near text "("; expecting ";", or ","
Error (10149): Verilog HDL Declaration error at imp.v(37): identifier "r1" is already declared in the present scope
Error (10170): Verilog HDL syntax error at imp.v(37) near text ")"; expecting ";", or ","
Error (10170): Verilog HDL syntax error at imp.v(38) near text "("; expecting ";", or ","
Error (10149): Verilog HDL Declaration error at imp.v(38): identifier "r1" is already declared in the present scope
Error (10170): Verilog HDL syntax error at imp.v(38) near text ")"; expecting ";", or ","
Error (10170): Verilog HDL syntax error at imp.v(49) near text "("; expecting ";", or ","
Error: Quartus II Analysis & Synthesis was unsuccessful. 19 errors, 7 warnings
Error: Peak virtual memory: 183 megabytes
Error: Processing ended: Thu May 10 10:45:19 2012
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:02
Error: Quartus II Full Compilation was unsuccessful. 21 errors, 7 warnings

---------- Post added at 06:23 ---------- Previous post was at 06:17 ----------

I have written code fro ROM where i hve stored image information and have separate code for RAM which is being modified depending on the operation carried out by sgmtnbox i.e. depends on its output decison

 

[FvM]

A general suggestion first. Get you a Verilog text book to understand about basic requirements of module design. Or review the Verilog template in Quartus code editor, accessible by a right mouse click.

You are trying to instantiate modules inside an always block. That's not possible according to Verilog rules. (Neither in VHDL, by the way).

 

[Gaurav Sarode]

@Fvm

I want to implement iterative operation on FPGA...and m not getting a way out of it pls help

---------- Post added at 08:00 ---------- Previous post was at 07:59 ----------

@Fvm

I want to implement iterative operation on FPGA...and m not getting a way out of it pls help

 

[FvM]

I fear, you have to go back to basic HDL design concepts first.

A for loop in HDL is not defining a sequence in time rather than parallel logic. Apart from other problems, the iteration construct in your code will generate 485 logic instances, which very likely execeeds any reasonable resource limits.

Module instances have to placed in concurrent code, outside laways blocks. To generate multiple instances in a loop, use a generate construct.

I guess, that th eintended iteration can be implemented as sequential processing, one iteration step per clock cycle. But I don't understand th eapplication problem in detail.

 

[Gaurav Sarode]

@FvMThanx for reply

I want to perform image segmentation for that i have to compare the pixel color value with all the other pixels color values, so i have saved the pixel color values in ROM and want to get following two tables from it here in first table H stands for population of frequency of that perticular RGB combination.

 

[Gaurav Sarode]

I have implemented it on MATLAB n now trying it on FPGA. Because repetitive comparison operation in algorithm m facing problem in it.
In MATLAB it was done with two nested for loops...

 

[Gaurav Sarode]

Is there any way to use designed hardware for operating on matrix saved in RAM on FPGA...

 

[FvM]

Data in RAM has to be accessed sequentially, one address per clock cycle.

 

[Gaurav Sarode]

how to do dat???

 

[atulaxc]

One of the good Verilog Tutorials I know will answer most of your basic Verilog questions. Its explained with many examples.

https://www.fullchipdesign.com/verilog_tutorial.htm

Synchronous Random Access Memory (RAM) implementation in verilog is at following link.

**broken link removed**

 

[Gaurav Sarode]

I want to store N*3 matrix on FPGA kit RAM i.e. dont want to geenerate hardware for it. and den access these matrix rows one by one pls help

 

[atulaxc]

With reference to sync_memory explanation on **broken link removed** You can infer RAM on fpgas by just removing the reset condition from the always block.**broken link removed** the memory is going to be inferred using logic cells.

 

[Gaurav Sarode]

hey thnx FvM n atulaxc i got the sequential accessing thing...

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hey thnx FvM n atulaxc i got the sequential accessing thing...