MRFGUY
Full Member level 1
modelsim expecting macromodule module primitive
Why this code is appear for me even simple verilog program. Every time I have to reopen .v file and find a lot of define (that I never key in) and delete.
the following is some of warning:
ARNING[10]: tbw.tfw(21): Bad name in macro definition: 3
# WARNING[10]: tbw.tfw(23): Bad name in macro definition: 7
# WARNING[10]: tbw.tfw(24): Bad name in macro definition: 4
# WARNING[10]: tbw.tfw(26): Bad name in macro definition: 7
# WARNING[10]: tbw.tfw(35): Bad name in macro definition: 4
# WARNING[10]: tbw.tfw(58): Bad name in macro definition: 1
# WARNING[10]: tbw.tfw(61): Bad name in macro definition: 7
# WARNING[10]: tbw.tfw(62): Bad name in macro definition: 9
Why this code is appear for me even simple verilog program. Every time I have to reopen .v file and find a lot of define (that I never key in) and delete.
the following is some of warning:
ARNING[10]: tbw.tfw(21): Bad name in macro definition: 3
# WARNING[10]: tbw.tfw(23): Bad name in macro definition: 7
# WARNING[10]: tbw.tfw(24): Bad name in macro definition: 4
# WARNING[10]: tbw.tfw(26): Bad name in macro definition: 7
# WARNING[10]: tbw.tfw(35): Bad name in macro definition: 4
# WARNING[10]: tbw.tfw(58): Bad name in macro definition: 1
# WARNING[10]: tbw.tfw(61): Bad name in macro definition: 7
# WARNING[10]: tbw.tfw(62): Bad name in macro definition: 9