error in model sim II 5.6e

modelsim expecting macromodule module primitive

Why this code is appear for me even simple verilog program. Every time I have to reopen .v file and find a lot of define (that I never key in) and delete.

the following is some of warning:

ARNING[10]: tbw.tfw(21): Bad name in macro definition: 3
# WARNING[10]: tbw.tfw(23): Bad name in macro definition: 7
# WARNING[10]: tbw.tfw(24): Bad name in macro definition: 4
# WARNING[10]: tbw.tfw(26): Bad name in macro definition: 7
# WARNING[10]: tbw.tfw(35): Bad name in macro definition: 4
# WARNING[10]: tbw.tfw(58): Bad name in macro definition: 1
# WARNING[10]: tbw.tfw(61): Bad name in macro definition: 7
# WARNING[10]: tbw.tfw(62): Bad name in macro definition: 9

Either u r using some reserved keywords for verilog or some kind of porting problem. Can u just paste ur code?

Sparc said:

Either u r using some reserved keywords for verilog or some kind of porting problem. Can u just paste ur code?

Click to expand...

It happen all the time. I just write new simple program and again it show so many defines.


Here is my program:
module test1(A, B, C, D, Y);

input A, B, C, D;
output Y;

assign Y = ((~A&~B&~C&~D)|(~A&~B&C&~D)|(~A&B&C&~D)|(A&~B&~C&~D)|(A&B&~C&~D)|(A&B&C&~D));

endmodule


Here is my errors:

# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# WARNING[10]: test1tbw.tfw(18): Bad name in macro definition: 6
# ERROR: test1tbw.tfw(18): near "nine": expecting: MACROMODULE MODULE PRIMITIVE (*
# WARNING[10]: test1tbw.tfw(21): Bad name in macro definition: 3
# WARNING[10]: test1tbw.tfw(23): Bad name in macro definition: 7
# WARNING[10]: test1tbw.tfw(24): Bad name in macro definition: 4
# WARNING[10]: test1tbw.tfw(26): Bad name in macro definition: 7
# WARNING[10]: test1tbw.tfw(35): Bad name in macro definition: 4
# WARNING[10]: test1tbw.tfw(58): Bad name in macro definition: 1
# WARNING[10]: test1tbw.tfw(61): Bad name in macro definition: 7
# WARNING[10]: test1tbw.tfw(62): Bad name in macro definition: 9
# WARNING[10]: test1tbw.tfw(65): Bad name in macro definition: 9
# WARNING[10]: test1tbw.tfw(67): Bad name in macro definition: 6
# WARNING[10]: test1tbw.tfw(69): Bad name in macro definition: 5
# WARNING[10]: test1tbw.tfw(73): Bad name in macro definition: 5e
# WARNING[10]: test1tbw.tfw(78): Bad name in macro definition: 7e
# WARNING[10]: test1tbw.tfw(84): Bad name in macro definition: 8
# WARNING[10]: test1tbw.tfw(92): Bad name in macro definition: 5
# WARNING[10]: test1tbw.tfw(95): Bad name in macro definition: 6
# WARNING[10]: test1tbw.tfw(97): Bad name in macro definition: 8
# WARNING[10]: test1tbw.tfw(101): Bad name in macro definition: 8
# WARNING[10]: test1tbw.tfw(102): Bad name in macro definition: 7
# WARNING[10]: test1tbw.tfw(103): Bad name in macro definition: 8
# WARNING[10]: test1tbw.tfw(104): Bad name in macro definition: 6
# WARNING[10]: test1tbw.tfw(110): Bad name in macro definition: 7
# WARNING[10]: test1tbw.tfw(121): Bad name in macro definition: 7
# WARNING[10]: test1tbw.tfw(123): Bad name in macro definition: 9
# WARNING[10]: test1tbw.tfw(124): Bad name in macro definition: 9
# WARNING[10]: test1tbw.tfw(137): Bad name in macro definition: 4
# WARNING[10]: test1tbw.tfw(142): Bad name in macro definition: 5
# WARNING[10]: test1tbw.tfw(150): Bad name in macro definition: 6
# WARNING[10]: test1tbw.tfw(151): Bad name in macro definition: 8
# WARNING[10]: test1tbw.tfw(152): Bad name in macro definition: 5
# WARNING[10]: test1tbw.tfw(156): Bad name in macro definition: 1
# WARNING[10]: test1tbw.tfw(157): Bad name in macro definition: 1
# WARNING[10]: test1tbw.tfw(159): Bad name in macro definition: 1
# WARNING[10]: test1tbw.tfw(160): Bad name in macro definition: 1
# WARNING[10]: test1tbw.tfw(161): Bad name in macro definition: 1
# WARNING[10]: test1tbw.tfw(162): Bad name in macro definition: 1
# WARNING[10]: test1tbw.tfw(164): Bad name in macro definition: 5
# WARNING[10]: test1tbw.tfw(165): Bad name in macro definition: 2
# WARNING[10]: test1tbw.tfw(166): Bad name in macro definition: 2
# WARNING[10]: test1tbw.tfw(167): Bad name in macro definition: 2
# WARNING[10]: test1tbw.tfw(168): Bad name in macro definition: 2
# WARNING[10]: test1tbw.tfw(169): Bad name in macro definition: 2
# WARNING[10]: test1tbw.tfw(171): Bad name in macro definition: 2
# WARNING[10]: test1tbw.tfw(172): Bad name in macro definition: 2
# WARNING[10]: test1tbw.tfw(173): Bad name in macro definition: 2e
# WARNING[10]: test1tbw.tfw(174): Bad name in macro definition: 2
# WARNING[10]: test1tbw.tfw(175): Bad name in macro definition: 3
# WARNING[10]: test1tbw.tfw(176): Bad name in macro definition: 3
# WARNING[10]: test1tbw.tfw(177): Bad name in macro definition: 3
# WARNING[10]: test1tbw.tfw(179): Bad name in macro definition: 3
# WARNING[10]: test1tbw.tfw(180): Bad name in macro definition: 3
# WARNING[10]: test1tbw.tfw(181): Bad name in macro definition: 3
# WARNING[10]: test1tbw.tfw(182): Bad name in macro definition: 3
# WARNING[10]: test1tbw.tfw(183): Bad name in macro definition: 3e
# WARNING[10]: test1tbw.tfw(184): Bad name in macro definition: 3
# WARNING[10]: test1tbw.tfw(185): Bad name in macro definition: 4
# WARNING[10]: test1tbw.tfw(186): Bad name in macro definition: 4
# WARNING[10]: test1tbw.tfw(187): Bad name in macro definition: 4
# WARNING[10]: test1tbw.tfw(188): Bad name in macro definition: 4
# WARNING[10]: test1tbw.tfw(190): Bad name in macro definition: 4
# WARNING[10]: test1tbw.tfw(191): Bad name in macro definition: 4
# WARNING[10]: test1tbw.tfw(192): Bad name in macro definition: 4e
# WARNING[10]: test1tbw.tfw(195): Bad name in macro definition: 1
# WARNING[10]: test1tbw.tfw(203): Bad name in macro definition: 6e
# WARNING[10]: test1tbw.tfw(204): Bad name in macro definition: 8
# WARNING[10]: test1tbw.tfw(206): Bad name in macro definition: 7
# WARNING[10]: test1tbw.tfw(212): Bad name in macro definition: 6
# WARNING[10]: test1tbw.tfw(213): Bad name in macro definition: 7
# WARNING[10]: test1tbw.tfw(215): Bad name in macro definition: 9
# WARNING[10]: test1tbw.tfw(217): Bad name in macro definition: 8
# WARNING[10]: test1tbw.tfw(219): Bad name in macro definition: 2
# WARNING[10]: test1tbw.tfw(221): Bad name in macro definition: 8
# WARNING[10]: test1tbw.tfw(223): Bad name in macro definition: 6
# WARNING[10]: test1tbw.tfw(224): Bad name in macro definition: 5
# WARNING[10]: test1tbw.tfw(225): Bad name in macro definition: 1e
# WARNING[10]: test1tbw.tfw(232): Bad name in macro definition: 9e
# WARNING[10]: test1tbw.tfw(239): Bad name in macro definition: 5
# WARNING[10]: test1tbw.tfw(245): Bad name in macro definition: 6
# WARNING[10]: test1tbw.tfw(246): Bad name in macro definition: 6
# WARNING[10]: test1tbw.tfw(250): Bad name in macro definition: 5
# WARNING[10]: test1tbw.tfw(251): Bad name in macro definition: 9
# WARNING[10]: test1tbw.tfw(261): Bad name in macro definition: 8
# WARNING[10]: test1tbw.tfw(263): Bad name in macro definition: 9
# WARNING[10]: test1tbw.tfw(264): Bad name in macro definition: 9
# WARNING[10]: test1tbw.tfw(274): Bad name in macro definition: 5
# WARNING[10]: test1tbw.tfw(277): Bad name in macro definition: 7
# WARNING[10]: test1tbw.tfw(282): Bad name in macro definition: 8e
# WARNING[10]: test1tbw.tfw(285): Bad name in macro definition: 9
# ERROR: c:/Modeltech_xe/win32xoem/vlog failed.
# Error in macro ./test1tbw.fdo line 7
# c:/Modeltech_xe/win32xoem/vlog failed.
# while executing
# "vlog -93 +libext+.v+.ve+ +define+OVI_Verilog+ test1tbw.tfw
# "

You have forgotten to declare what type (reg or wire) A, B, C, D, Y are and if they are buses or not.

adap said:

You have forgotten to declare what type (reg or wire) A, B, C, D, Y are and if they are buses or not.

Click to expand...

I don't think I have to declare Reg or wire for A, B C and D (because they are just input ports, and I think for Y if I use assign I no need to declare as Reg).

If this is ur only code, then there is no problem in ur code, it's working fine with me on both ModelSim6.0a awa ModelSim5.7e. What is your TestBench?

You are trying to compile ur code with OVL lib it seems!
Please Check!
Try out simple following command

vlog test1.v

Where test1.v contains ur code you posted here!!

Here is my testbench.

nand_gates said:

You are trying to compile ur code with OVL lib it seems!
Please Check!
Try out simple following command

vlog test1.v

Where test1.v contains ur code you posted here!!

Click to expand...

The results:

vlog test1.v
# Model Technology ModelSim XE II vlog 5.6e Compiler 2002.10 Oct 22 2002
# -- Compiling module test1
#
# Top level modules:
# test1

Hi,
I got the problem. Here I am sending the corrected testcode. I deleted
the useless file test1tbw.tbw!
Unrar it and run it using following steps

1. vlib work
2. vlog test1.v test1tbw.tfw
3. vsim testbench &
4. At vsim prompt give following command
source a.do
5. Done!