Error in designing a 5bit binary to thermometer decoder in Verilog

[sal_]

a net is not a legal lvalue in this context

Hi guys, would be very appreciative of any help anyone can give. I'm trying to design a 5bit binary to thermometer decoder for use in a 10bit segmented current DAC.

//Verilog HDL for "lablib", "ee435" "behavioral"

module ee435 (bin, thermometer);

input [4:0] bin;
reg [4:0] breg;

always @ (bin)
begin
breg = bin;
case (breg)

5'b00000: thermometer = 31'b0000000000000000000000000000000;
5'b00001: thermometer = 31'b0000000000000000000000000000001;
5'b00010: thermometer = 31'b0000000000000000000000000000011;
5'b00011: thermometer = 31'b0000000000000000000000000000111;
5'b00100: thermometer = 31'b0000000000000000000000000001111;
5'b00101: thermometer = 31'b0000000000000000000000000011111;
5'b00110: thermometer = 31'b0000000000000000000000000111111;
5'b00111: thermometer = 31'b0000000000000000000000001111111;
5'b01000: thermometer = 31'b0000000000000000000000011111111;
5'b01001: thermometer = 31'b0000000000000000000000111111111;
5'b01010: thermometer = 31'b0000000000000000000001111111111;
5'b01011: thermometer = 31'b0000000000000000000011111111111;
5'b01100: thermometer = 31'b0000000000000000000111111111111;
5'b01101: thermometer = 31'b0000000000000000001111111111111;
5'b01110: thermometer = 31'b0000000000000000011111111111111;
5'b01111: thermometer = 31'b0000000000000000111111111111111;
5'b10000: thermometer = 31'b0000000000000001111111111111111;
5'b10001: thermometer = 31'b0000000000000011111111111111111;
5'b10010: thermometer = 31'b0000000000000111111111111111111;
5'b10011: thermometer = 31'b0000000000001111111111111111111;
5'b10100: thermometer = 31'b0000000000011111111111111111111;
5'b10101: thermometer = 31'b0000000000111111111111111111111;
5'b10110: thermometer = 31'b0000000001111111111111111111111;
5'b10111: thermometer = 31'b0000000011111111111111111111111;
5'b11000: thermometer = 31'b0000000111111111111111111111111;
5'b11001: thermometer = 31'b0000001111111111111111111111111;
5'b11010: thermometer = 31'b0000011111111111111111111111111;
5'b11011: thermometer = 31'b0000111111111111111111111111111;
5'b11100: thermometer = 31'b0001111111111111111111111111111;
5'b11101: thermometer = 31'b0011111111111111111111111111111;
5'b11110: thermometer = 31'b0111111111111111111111111111111;
5'b11111: thermometer = 31'b1111111111111111111111111111111;

endcase
end
endmodule

The error that appears when im trying to parse is:

ncvlog: *E,WANOTL (/home/lablib/ee435/behavioral/verilog.v, 16|20): a net is not a legal lvalue in this context [9. 3. 1. (IEEE) ]. 5'b00001: thermometer = 31'b0000.....;

for all my case statements. I'm pretty new to verilog so i expect it's something basic, cheers guys!

 

[dcreddy1980]

wanotl

output[30:0] thermometer;
reg[30:0] thermometer;

The above statements are missing, if you don't declare thermometer o/p, it will treated as wire which is not you wanted by looking at your code.

 

[chenbintom]

e,wanotl

thermometer should declare as "reg"

 

[sal_]

binary to termometer decoder

thanks guys, worked a treat!