Error in concept hdl schmeatic

Hi all,

i got errors while checking the ERC rule . please refer the attached error and give me a solution





Cadence Design Systems, Inc.
Packager-XL 16.6-S048 (v16-6-112DX) WIN32 4/13/2015 12:00:00 IST
(C) Copyright 1994, Cadence Design Systems, Inc.

Run on Tue Sep 22 09:56:23 2015


**********************************************
* Processing project file and command line *
**********************************************



ANNOTATE 'BODY' 'PIN'
COMP_DEF_PROP 'ALT_SYMBOLS' 'JEDEC_TYPE' 'MERGE_NC_PINS' 'MERGE_POWER_PINS'
'NC_PINS' 'POWER_GROUP' 'POWER_PINS' 'SIGNAL_MODEL' 'VALUE'
'TOLERANCE' 'TECHNOLOGY' 'TACC' 'VOLTAGE' 'REFERENCE' 'BOI'
'PART_NUMBER'
COMP_INST_PROP 'PART_NUMBER' 'GROUP' 'REUSE_ID' 'REUSE_INSTANCE'
'REUSE_NAME' 'ROOM' 'BOM_IGNORE' 'ISRFELEMENT'
'RFELEMENTTYPE' 'RFLAYER' 'RFLAYER1' 'RFLAYER2' 'RFLAYER3'
'RFLAYER4' 'RFLAYER5' 'RFLAYER6' 'RFLAYER7' 'RFLAYER8'
'RFLAYER9' 'RFLAYER10' 'RFLAYER11' 'RFLAYER12' 'RFLAYER13'
'RFLAYER14' 'RFLAYER15' 'RFLAYER16' 'RFCOUPLINGMODE'
'RFFLIPMODE' 'RFANGLE' 'RFANGLE1' 'RFWIDTH' 'RFWIDTH1'
'RFWIDTH2' 'RFWIDTH3' 'RFWIDTH4' 'RFWIDTH5' 'RFWIDTH6'
'RFWIDTH7' 'RFWIDTH8' 'RFWIDTH9' 'RFWIDTH10' 'RFWIDTH11'
'RFWIDTH12' 'RFWIDTH13' 'RFWIDTH14' 'RFWIDTH15' 'RFWIDTH16'
'RFLENGTH' 'RFLENGTH1' 'RFLENGTH2' 'RFLENGTH3' 'RFLENGTH4'
'RFLENGTH5' 'RFLENGTH6' 'RFLENGTH7' 'RFLENGTH8' 'RFSPACING'
'RFSPACING1' 'RFSPACING2' 'RFSPACING3' 'RFSPACING4'
'RFSPACING5' 'RFSPACING6' 'RFSPACING7' 'RFSPACING8'
'RFSPACING9' 'RFSPACING10' 'RFSPACING11' 'RFSPACING12'
'RFSPACING13' 'RFSPACING14' 'RFSPACING15' 'RFOFFSETX'
'RFOFFSETY' 'RFRADIUS' 'RFDEPTH' 'RFFREQUENCY'
'RFMITERFRACTION' 'RFBENDMODE' 'RFNUMBERLEGS'
'RFNUMBERPAIRS' 'RFNUMBERTURNS' 'RFCAPACITANCE'
'RFRESISTANCE' 'RFINDUCTANCE' 'RFPADSTACKNAME'
'RFPADSSMNAME1' 'RFPADSSMNAME2' 'RFPADBEGINLAYER'
'RFPADENDLAYER' 'RFPADLINEWIDTH1' 'RFPADLINEWIDTH2'
'RFPADDIAMETER1' 'RFPADDIAMETER2' 'RFPADLENGTH1'
'RFPADLENGTH2' 'RFHOLEDIAMETER' 'RFPADANGLE' 'RFDRANAME'
'RFPADTYPE' 'RFUID' 'RFBLOCK' 'RFDCNET' 'RFGROUP' 'MWO_NAME'
'SIGNAL_MODEL' 'DEFAULT_SIGNAL_MODEL'
'VOLT_TEMP_SIGNAL_MODEL' 'CDS_FSP_LIB_PART_MODEL'
'CDS_FSP_IS_FPGA' 'CDS_FSP_INSTANCE_NAME'
'CDS_FSP_INSTANCE_ID'
SUPPRESS_GLOBAL_SHORT_CHECK OFF
DEBUG 0
DEFAULT_PHYS_DES_PREFIX U
FEEDBACK 'OFF'
MAX_ERRORS 999
NET_NAME_CHARS @ - ! # % & ( ) * . / : ? [ ] ^ _ ` +
= > 0 1 2 3 4 5 6 7 8 9
NET_NAME_LENGTH 31
NUM_OLD_VERSIONS 3
OPTIMIZE OFF
REUSE_REFDES ON
OPF_OPTIMIZATION OFF
HARD_LOC_SEC OFF
FORCE_PTF_ENTRY OFF
REGENERATE_PHYSICAL_NET_NAME OFF
SCH_POWER_GROUP_WINS_OVER_PPT OFF
NULL_OPT_VALID OFF
USE_VECTOR_NOTATION ON
FILTER_ECS_FROM_XNET ON
OUTPUT 'ON'
PACKAGE_PROP 'GROUP' 'ROOM'
PART_TYPE_LENGTH 31
REF_DES_LENGTH 31
REPACKAGE OFF
ELECTRICAL_CONSTRAINTS ON
OVERWRITE_CONSTRAINTS OFF
RUN_DIR ./worklib/top/packaged/
USE_LIBRARY_PPT ON
USE_STATE ON
WARNINGS ON
LIBRARY 'design_lib' 'ecad_lib' 'ecad_lib_local' 'standard'
VIEW_PTF part_table
VIEW_PACKAGER packaged
VIEW_CONSTRAINTS sch_1
DESIGN_LIBRARY design_lib
DESIGN_NAME top
VIEW_CONFIG_PHYSICAL cfg_package
SD_SUFFIX_SEPARATOR _
STOP_PST_GEN_ON_PTF_MISMATCH ON
IGNORE_PRIM_BINDING OFF
LOG_INST_PHYS_PATH ON
ANNOTATE_VISIBLE_SEC OFF
PTF_MISMATCH_EXCLUDE_INJ_PROP 'ALL'
IMPORT_HFS_HARDSEC_ON_SWAP_PINS OFF
ALLOW_PTFVALUE_INITIAL_BLANKS ON
PRESERVE_UNSUBSTITUTED_MACROS OFF
DETECT_SYS_NETSHORTS_PKG ON
PROCESS_PIN_SHORT_PROP OFF
STOP_PACKAGE_ON_SCHEMATIC_ERROR OFF
LOCK_FILE_PERM 444
LOCK_FOR_SAME_USER OFF
ERROR_ON_MISMATCHED_INTERFACE ON
RETAIN_ZERO_NODE_NETS OFF
IGNORE_ERR_EMPTY_LONGPARTNAME OFF
ERROR_ILLEGAL_QUOTE_PPT OFF
B2F_OVERWRITE_CONSTRAINTS OFF
ERROR_ON_PARTIAL_INSTANTIATION_OF_HSS OFF
RUN_HIERWR_BEFORE_PXL OFF
IMPORT_CONSTRAINTS_ONLY_FEEDBACK OFF

**************************************************************
* End processing project file and command line (00:00:02) *
**************************************************************


Creating Configuration "cfg_package" for Design "top"

INFO(SPCODD-181): Loading C:\CAD_APPS\Cadence\SPB_16.6\share\cdssetup\cdsprop.~
tmf.
INFO(SPCODD-181): Loading C:\CAD_APPS\Cadence\SPB_16.6\share\cdssetup\cdsprop.~
paf.

*********************************
* Loading the design database *
*********************************

INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/cppm/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/rbob/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/con3/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/con4/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/con34/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/con6/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/rcm/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/dled/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/probe/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/diod/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/calu/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/diod2ak/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/cer/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/regso8/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/lm393/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/tp/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/hc132/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/shunt/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/hc14/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/lm555/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/dzen/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/tmn/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/uln2003/part_table/phys.ptf.
INFO(SPCODD-181): Loading y:/DATA/ecad_lib/body/reg/part_table/phys.ptf.

*************************
* Loading State Files *
*************************

State file pxl.state not loaded because not found.

*****************************************
* End loading State Files (00:00:00) *
*****************************************


****************************************
* Starting to assign physical parts. *
****************************************


***********************************************
* End assigning physical parts. (00:00:00) *
***********************************************


***************
* Packaging *
***************

#1 ERROR(SPCOPK-1109): Cannot package instance into package VD6.
Schematic instance: @DESIGN_LIB.TOP(SCH_1)AGE6_I13@ECAD_LIB.DIOD2AK(~
CHIPS) (MODULE: TOP; PART: DIOD2AK)
Physical Path: @design_lib.top(sch_1)age6_i13@ecad_lib.diod2ak(chips)
The instances have the same location property value. Change the locati~
on property value for any one of the instances in the Design Entry HDL Schemat~
ic.
#2 ERROR(SPCOPK-1422): Section 1, common pin X is connected to different ne~
ts:
Schematic net: @DESIGN_LIB.TOP(SCH_1):UNNAMED_6_CER_I7_B
Package net: @DESIGN_LIB.TOP(SCH_1):UNNAMED_6_DIOD2AK_I13_A
Package net: @DESIGN_LIB.TOP(SCH_1)AGE6_I14@ECAD_LIB.DIOD2AK(CHIPS) ~
(MODULE: TOP; PART: DIOD2AK)
Physical Path: @design_lib.top(sch_1)age6_i14@ecad_lib.diod2ak(chips)
Packaged instance: 
#3 ERROR(SPCODD-101): Primitive @DESIGN_LIB.TOP(SCH_1)AGE6_I13@ECAD_LIB.D~
IOD2AK(CHIPS) is not packaged.
#4 ERROR(SPCODD-100): State file not written for design TOP.
INFO(SPCOPK-1441): 4 errors detected
INFO(SPCOPK-1444): No warnings detected
INFO(SPCOPK-1448): Use Tools->Markers->Packager in ConceptHDL to highlight ins~
tances for the errors/warnings reported.
Start time 9:56:17
End time 9:56:57
Elapsed time 0:00:40

**************************************************
* FATAL ERROR PackagerXL exiting with status 2 *
**************************************************