abimann
Member level 4
Dear all Gurus and just good guys!
Pls tell me what's wrong with my code, top level file is in VHDL , lower level file is Verilog,why i get this kind of error ?
I remember that VHDL and Verilog works well in my old projects and this is not reason.
Pls tell me what's wrong with my code, top level file is in VHDL , lower level file is Verilog,why i get this kind of error ?
I remember that VHDL and Verilog works well in my old projects and this is not reason.
Code:
ERROR:HDLParsers:709 - "C:/Users/user1/Desktop/fpga_p/MT9/camera_v0.vhd" Line 229. Reset_Delay is not an entity name
signal DLY_RST_1, DLY_RST_0,DLY_RST_2: std_logic;
U1: entity work.Reset_Delay
PORT MAP( iCLK => clk96,
iRST => rst_n,
oRST_0 => DLY_RST_0,
oRST_1 => DLY_RST_1,
oRST_2 => DLY_RST_2 );
module Reset_Delay(iCLK,iRST,oRST_0,oRST_1,oRST_2);
input iCLK;
input iRST;
output reg oRST_0;
output reg oRST_1;
output reg oRST_2;