Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

error dumping fsdb on gate simulation

Status
Not open for further replies.

unmay7

Newbie
Newbie level 1
Joined
Nov 1, 2022
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
12
Hi,

I am trying to dump fsdb waveform using below code and it works fine on RTL design but gives an error on Gate simulation.

Code:
--------------

  initial begin
      #5000ns;
      $fsdbDumpfile("waveform_B.fsdb");
      $fsdbDumpvars(0,"tb_uvm_design.dut");
      #1000ns;
      $fsdbDumpoff;
  end



ERROR
--------------
Dumping Waveforms Now - VCD & FSDB
FSDB Dumper for ModelSim, Release Verdi_Q-2020.03-SP2, Linux x86_64/64bit, 08/31/2020
(C) 1996 - 2020 by Synopsys, Inc.
***********************************************************************
*  WARNING -                                                          *
*  The simulator version is newer than the supported FSDB Writer.     *
***********************************************************************
*Verdi* : Create FSDB file 'waveform_B.fsdb'
*Verdi* : Begin traversing the scope (tb_uvm_design.dut), layer (0).
*Verdi* : End of traversing.
*Verdi* FSDB: For performance reasons, the Memory Size Limit has been increased to 512M.
*Verdi* FSDB: For performance reasons, the Memory Size Limit has been increased to 1024M.
# Attempting stack trace sig 11
# Signal caught: signo [11]
# vsim_stacktrace.vstf written
# Current time Tue Nov  1 13:27:23 2022
# Program = vsim
# Id = "2019.4_3"
# Version = "2020.02"
# Date = "Feb 26 2020"
# Platform = "linux_x86_64"
# Signature = 1ce5d4bb2240a7b76b673fefbfff0329
# 0    0x000000000057db33: '<unknown (@0x57db33)>'
# 1    0x0000000000591399: '<unknown (@0x591399)>'
# 2    0x00000000004f5da9: '<unknown (@0x4f5da9)>'
# 3    0x000000000068d703: '<unknown (@0x68d703)>'
# 4    0x0000000000b99963: '<unknown (@0xb99963)>'
# 5    0x0000000000b9e2ab: '<unknown (@0xb9e2ab)>'
# 6    0x0000000000b9ffde: '<unknown (@0xb9ffde)>'
# 7    0x0000000000e5bd7d: '<unknown (@0xe5bd7d)>'
# 8    0x000000000159f98d: '<unknown (@0x159f98d)>'
# 9    0x00000000015a3de6: '<unknown (@0x15a3de6)>'
# 10   0x00000000015a54d1: '<unknown (@0x15a54d1)>'
# 11   0x00000000015a5836: '<unknown (@0x15a5836)>'
# 12   0x00000000015a6f53: '<unknown (@0x15a6f53)>'
# 13   0x00000000015a7711: '<unknown (@0x15a7711)>'
# 14   0x0000000000b6f9b0: '<unknown (@0xb6f9b0)>'
# 15   0x0000000000b7107a: '<unknown (@0xb7107a)>'
# End of Stack Trace


** Fatal: (SIGSEGV) Bad pointer access. Closing vsimk.
** Fatal: vsimk is exiting with code 211.
Exit codes are defined in the "Error and Warning Messages"
appendix of the QuestaSim User's Manual.
 
Last edited by a moderator:

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top