Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Error: Clock tree synthesis in Encounter 10.1

Status
Not open for further replies.

sudeep_

Member level 1
Joined
Jul 31, 2013
Messages
40
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
261
Hi,

I am getting an error while doing clock tree synthesis in encounter 10.1. It showing that
**ERROR: (ENCCK-158): Cannot find output terms for clock clk_in/ANAIO.

Here pad inastant name is "clk_in" and pin name is "ANAIO".


CLock tree specifile started like

AutoCTSRootPin clock clk_in/ANAIO
 

sid_27

Junior Member level 2
Joined
Aug 14, 2013
Messages
21
Helped
6
Reputation
12
Reaction score
6
Trophy points
3
Activity points
139
I guess this question is related to ASIC if I am not wrong, You should post this question in the other forum named: ASIC Design Methodologies and Tools (Digital). You could get help more quickly.

Regards
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top