Error : "Cannot connect a VHDL scalar signal to Verilog vector port" in Modelsim

Cesar0182 said:

Greetings, let you know that I have found an example of an asynchronous fifo in verilog and I have implemented it to my vhdl project in Vivado 20192.2 but I am having problems trying to simulate it in Modelsim SE 10.5. I am getting the following error from the image.

View attachment 172431
Could someone help me with this problem please, I leave part of the fifo code and how I am trying to implement it in my project.

FIFO Code:

Code:

`timescale 1ns / 1ps

module l1_spi_async_fifo_slv#(
    parameter DATA_WIDTH = 1,
    parameter DATA_DEPTH = 1024
    )(
    input wr_clk,
    input wr_rst,
    input wr_en,
    input [DATA_WIDTH - 1 : 0] wr_data,
    output reg full,

    input rd_clk,
    input rd_rst,
    input rd_en,
    output reg [DATA_WIDTH - 1 : 0] rd_data,
    output reg empty

    );

Main code:

Code:

slv_mosi_miso_ff_arst                        : std_logic;
spi_clk_syn                                    : std_logic;
tx_byte_to_bit                                : std_logic;
tx_bit_length_wr                            : std_logic;
fifo_rd_bits_en                                : std_logic;
signal rd_data_slv_f1                       : std_logic;
signal empty_slv_f1                         : std_logic;
signal full_slv_f1                          : std_logic;

u_spi_async_fifo_slv_f1 : entity work.l1_spi_async_fifo_slv
    generic map(
    DATA_WIDTH => 1,
    DATA_DEPTH => 1024)
  PORT MAP(
    wr_rst      => slv_mosi_miso_ff_arst,
    rd_rst      => slv_mosi_miso_ff_arst,
    wr_clk      => i_clk_25Mhz,
    rd_clk      => spi_clk_syn,
    wr_data     => tx_byte_to_bit,
    wr_en       => tx_bit_length_wr,
    rd_en       => fifo_rd_bits_en,
    rd_data     => rd_data_slv_f1,
    full        => full_slv_f1,
    empty       => empty_slv_f1
  );

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