well then i tried the following
include mux_using_assign.v ;
module test_mux ;
wire t_mux_out;
reg t_din_0,t_din_1,t_sel;
mux_using_assign dut(t_din_0,t_din_1,sel,t_mux_out);
/*mux_using_assign(
.din_0(t_din_0),
.din_1(t_din_1),
.sel(t_sel),
.mux_out(t_mux_out)
);*/
initial
begin
t_din_0 = 0; t_din_1 = 0; t_sel = 0;
#10
t_sel = 1;
$finish;
end
initial
$monitor($time,,t_mux_out,,t_din_0,,t_din_1,,t_sel);
endmodule
vsim work.test_mux
# vsim work.test_mux
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Warning: t_mux.v(6): [TFMPC] - Too few port connections for 'dut'. Expected 5, found 4.
# Loading work.test_mux(fast)
???????
---------- Post added at 23:43 ---------- Previous post was at 22:51 ----------
then i modified it again
include mux_using_assign.v ;
module test_mux ;
wire mux_out;
reg din_0,din_1,sel;
mux_using_assign dut(din_0,din_1,sel,mux_out);
/*mux_using_assign(
.din_0(t_din_0),
.din_1(t_din_1),
.sel(t_sel),
.mux_out(t_mux_out)
);*/
initial
begin
din_0 = 0; din_1 = 0; sel = 0;
#50
sel = 1;
#100 $stop;
end
initial
$monitor($stime,,mux_out,,din_0,,din_1,,sel);
endmodule
vsim work.test_mux
# vsim work.test_mux
# ** Note: (vsim-3812) Design is being optimized...
# ** Warning: t_mux.v(6): [TFMPC] - Too few port connections for 'dut'. Expected 5, found 4.
# Loading work.test_mux(fast)
the above modification is due to the fact that it is the out put of the blackbox design that we should be analyzing in the waveform viewer, and not the output of the testbench(which essentially is the input to the design under test(hence din_0 etc, the input to the dut are taken as wire and not the usual reg reserved for inputs)
however
1)iam getting this warning
2)modelsim is not printing the signals in object view