Mysterion
Newbie
Hello everyone,
So I'm trying to implement a shift R/L register using a d_ff component (asynchronous low active reset, asynchronous set), but I'm getting this error
Can you tell me please what I'm doing wrong and how I can fix it ? Thank you in advance for your help
Here the code for the d_FF:
and here for the shift_register:
[Moderator added code tags]
So I'm trying to implement a shift R/L register using a d_ff component (asynchronous low active reset, asynchronous set), but I'm getting this error
Error (10028): Can't resolve multiple constant drivers for net "dout[3]" at bi_shiftReg_ff.vhd(58)
Error (10029): Constant driver at bi_shiftReg_ff.vhd(101)
Error (10028): Can't resolve multiple constant drivers for net "dout[2]" at bi_shiftReg_ff.vhd(51)
Error (10028): Can't resolve multiple constant drivers for net "dout[1]" at bi_shiftReg_ff.vhd(44)
Error (10028): Can't resolve multiple constant drivers for net "dout[0]" at bi_shiftReg_ff.vhd(37)
Can you tell me please what I'm doing wrong and how I can fix it ? Thank you in advance for your help
Here the code for the d_FF:
Code:
library ieee;
use ieee.std_logic_1164.all;
entity d_flipflop is
port( d, clk, set, n_reset: in std_logic;
q: out std_logic
);
end d_flipflop;
architecture arch of d_flipflop is
signal temp: std_logic;
begin
process(clk,set,n_reset,temp)
begin
if n_reset = '0' then
temp <= '0';
elsif set = '1' then
temp <= '1';
elsif rising_edge(clk) then
temp <= d;
end if;
q <= temp;
end process;
end arch;
and here for the shift_register:
Code:
library ieee;
use ieee.std_logic_1164.all;
entity bi_shiftReg_ff is
port( din: in std_logic_vector(3 downto 0);
set, n_reset: in std_logic;
sR, sL: in std_logic; -- Shift-Right/Shift-Left
data_load: in std_logic;
clk: in std_logic;
dout: inout std_logic_vector(3 downto 0);
s_dout_R: out std_logic; -- Shift-Right output
s_dout_L: out std_logic -- Shift-Left output
);
end bi_shiftReg_ff;
architecture arch of bi_shiftReg_ff is
component d_flipflop is
port( d, clk, set, n_reset: in std_logic;
q, qn: out std_logic
);
end component;
begin
u0: d_flipflop
port map ( d => din(0),
clk => clk,
set => set,
n_reset => n_reset,
q => dout(0)
);
u1: d_flipflop
port map ( d => din(1),
clk => clk,
set => set,
n_reset => n_reset,
q => dout(1)
);
u2: d_flipflop
port map ( d => din(2),
clk => clk,
set => set,
n_reset => n_reset,
q => dout(2)
);
u3: d_flipflop
port map ( d => din(3),
clk => clk,
set => set,
n_reset => n_reset,
q => dout(3)
);
process(clk, data_load)
begin
if(rising_edge(clk) and data_load = '1') then
s_dout_R <= din(0);
s_dout_L <= din(3);
-- shift right
if(rising_edge(clk) and sR = '1') then
--s_dout_R <= dout(0);
dout(2 downto 0) <= dout(3 downto 1);
-- shift left
elsif(rising_edge(clk) and sL = '1') then
--s_dout_L <= dout(3);
dout(3 downto 1) <= dout(2 downto 0);
end if;
end if;
end process;
end arch;