[SOLVED] Error 10028

[Mysterion]

Hello everyone,
So I'm trying to implement a shift R/L register using a d_ff component (asynchronous low active reset, asynchronous set), but I'm getting this error

Error (10028): Can't resolve multiple constant drivers for net "dout[3]" at bi_shiftReg_ff.vhd(58)
Error (10029): Constant driver at bi_shiftReg_ff.vhd(101)
Error (10028): Can't resolve multiple constant drivers for net "dout[2]" at bi_shiftReg_ff.vhd(51)
Error (10028): Can't resolve multiple constant drivers for net "dout[1]" at bi_shiftReg_ff.vhd(44)
Error (10028): Can't resolve multiple constant drivers for net "dout[0]" at bi_shiftReg_ff.vhd(37)

Can you tell me please what I'm doing wrong and how I can fix it ? Thank you in advance for your help
Here the code for the d_FF:

library ieee;
use ieee.std_logic_1164.all;

entity d_flipflop is
    port( d, clk, set, n_reset: in std_logic;
            q: out std_logic
            );
end d_flipflop;

architecture arch of d_flipflop is
signal temp: std_logic;
begin
    process(clk,set,n_reset,temp)
 
    begin
         if n_reset = '0' then
            temp <= '0';
         elsif set = '1' then
            temp <= '1';
         elsif rising_edge(clk) then
            temp <= d;
         end if;
    q <= temp;
    end process;
end arch;

and here for the shift_register:

library ieee;
use ieee.std_logic_1164.all;

entity bi_shiftReg_ff is
    port( din: in std_logic_vector(3 downto 0);
            set, n_reset: in std_logic;
            sR, sL: in std_logic; -- Shift-Right/Shift-Left
            data_load: in std_logic;
            clk: in std_logic;
            dout: inout std_logic_vector(3 downto 0);
            s_dout_R: out std_logic; -- Shift-Right output
            s_dout_L: out std_logic -- Shift-Left output
            );
end bi_shiftReg_ff;

architecture arch of bi_shiftReg_ff is

    component d_flipflop is
        port( d, clk, set, n_reset: in std_logic;
                q, qn: out std_logic
                );
    end component;
begin
 
    u0: d_flipflop
        port map ( d => din(0),
                      clk => clk,
                      set => set,
                      n_reset => n_reset,
                      q => dout(0)
                        );
    u1: d_flipflop
        port map ( d => din(1),
                      clk => clk,
                      set => set,
                      n_reset => n_reset,
                      q => dout(1)
                        );
    u2: d_flipflop
        port map ( d => din(2),
                      clk => clk,
                      set => set,
                      n_reset => n_reset,
                      q => dout(2)
                        );
    u3: d_flipflop
        port map ( d => din(3),
                      clk => clk,
                      set => set,
                      n_reset => n_reset,
                      q => dout(3)
                        );
process(clk, data_load)
 
        begin
                if(rising_edge(clk) and data_load = '1') then
                    s_dout_R <= din(0);
                    s_dout_L <= din(3);
                -- shift right
                    if(rising_edge(clk) and sR = '1') then
                    --s_dout_R <= dout(0);
                    dout(2 downto 0) <= dout(3 downto 1); 
                -- shift left
                    elsif(rising_edge(clk) and sL = '1') then
                    --s_dout_L <= dout(3);
                    dout(3 downto 1) <= dout(2 downto 0);
                    end if;
                end if;
        end process;
    
end arch;

[Moderator added code tags]

 

[FvM]

You are driving dout in two places, the dff instances and in the process at the bottom. That's not feasible. If you want to drive dout alternatively depending on a condition, you need a mux or something similar. Rethink the intended design function.

If you put a behavioral description of the dff function into the process, it becomes much easier to handle the alternative sources of dout.

By the way, it makes no sense to define dout as inout port.

 

[Mysterion]

Thanks a lot for your answer !
I did try another way but this time I'm not getting my dout updated when there is a shift. any idea how to fix it ?

library ieee;
use ieee.std_logic_1164.all;

entity bi_shiftReg_ff is
    port( din: in std_logic_vector(3 downto 0);
            set, n_reset: in std_logic;
            sR, sL: in std_logic; -- Shift-Right/Shift-Left
            data_load: in std_logic;
            clk: in std_logic;
            dout: out std_logic_vector(3 downto 0);
            s_dout_R: out std_logic; -- Shift-Right output
            s_dout_L: out std_logic -- Shift-Left output
            );
end bi_shiftReg_ff;

architecture arch of bi_shiftReg_ff is

    component four_dff is
        port( d: in std_logic_vector(3 downto 0);
                clk, set, n_reset: in std_logic;
                q: out std_logic_vector(3 downto 0)
                );
    end component;
      
    signal s1: std_logic_vector(3 downto 0);
    signal s2: std_logic_vector(3 downto 0);
   
begin
   
    u: four_dff
        port map( d => din,
                     clk => clk,
                     set => set,
                     n_reset => n_reset,
                     q => dout
                        );

    s1 <= din;
   
    process(clk, data_load)
   
        begin
                if(rising_edge(clk) and data_load = '1') then
                    s_dout_R <= s1(0);
                    s_dout_L <= s1(3);
                    s2 <= s1;
                -- shift right
                    if(rising_edge(clk) and sR = '1') then
                    --s_dout_R <= dout(0);
                    s2(2 downto 0) <= s2(3 downto 1);   
                -- shift left
                    elsif(rising_edge(clk) and sL = '1') then
                    --s_dout_L <= dout(3);
                    s2(3 downto 1) <= s2(2 downto 0);
                    end if;
                end if;
        end process;
end arch;[code]

[ATTACH type="full" width="920px"]174013[/ATTACH]

 

[Mysterion]

Here an implementation whitout using any mux, maybe it will help someone in the future

-- bidirektionale shift register mit data-load und serielle(R/L) output mit D-ff

library ieee;
use ieee.std_logic_1164.all;

entity bi_shiftReg_ff is
    port( din: in std_logic_vector(3 downto 0);
            set, n_reset: in std_logic;
            sR, sL: in std_logic; -- Shift-Right/Shift-Left
            data_load: in std_logic;
            clk: in std_logic;
            dout: out std_logic_vector(3 downto 0);
            s_dout_R: out std_logic; -- Shift-Right output
            s_dout_L: out std_logic -- Shift-Left output
            );
end bi_shiftReg_ff;

architecture arch of bi_shiftReg_ff is

    -- FF component
  component d_flipflop is
    port(d, clk, set, n_reset : in  std_logic;
         q: out std_logic
         );
  end component;
    
    -- FF data input
   signal d : std_logic_vector(3 downto 0);

   -- FF data output
   signal q : std_logic_vector(3 downto 0);
       
begin
    -- Kombinatorisches Verfahren, so dass Gates nur
    process (all)
        begin
            -- data-load
            if (data_load = '1') then
                d <= din;
                s_dout_R <= din(din'right); -- LSB
                s_dout_L <= din(din'left); -- MSB
            -- shift right;
            elsif (sR = '1') then
                d <= '0' & q(q'left downto 1);  -- Verwerfen des Bits ganz rechts in der rechten Verschiebung
            -- shift left
            elsif (sL = '1') then
                d <= q(q'left - 1 downto 0) & '0';  -- Verwerfen des Bits ganz links in der linken Verschiebung
            end if;
    end process;

  -- Zustand im Flipflops gehalten
  GEN_REG : for i in 0 to 3 generate
    REGX : d_flipflop port map
      (d(i), clk, set, n_reset, q(i));
  end generate;

  -- Outputs drive
  dout <= q;
[code]