library ieee;
use ieee.std_logic_1164.all;
entity bi_shiftReg_ff is
port( din: in std_logic_vector(3 downto 0);
set, n_reset: in std_logic;
sR, sL: in std_logic; -- Shift-Right/Shift-Left
data_load: in std_logic;
clk: in std_logic;
dout: inout std_logic_vector(3 downto 0);
s_dout_R: out std_logic; -- Shift-Right output
s_dout_L: out std_logic -- Shift-Left output
);
end bi_shiftReg_ff;
architecture arch of bi_shiftReg_ff is
component d_flipflop is
port( d, clk, set, n_reset: in std_logic;
q, qn: out std_logic
);
end component;
begin
u0: d_flipflop
port map ( d => din(0),
clk => clk,
set => set,
n_reset => n_reset,
q => dout(0)
);
u1: d_flipflop
port map ( d => din(1),
clk => clk,
set => set,
n_reset => n_reset,
q => dout(1)
);
u2: d_flipflop
port map ( d => din(2),
clk => clk,
set => set,
n_reset => n_reset,
q => dout(2)
);
u3: d_flipflop
port map ( d => din(3),
clk => clk,
set => set,
n_reset => n_reset,
q => dout(3)
);
process(clk, data_load)
begin
if(rising_edge(clk) and data_load = '1') then
s_dout_R <= din(0);
s_dout_L <= din(3);
-- shift right
if(rising_edge(clk) and sR = '1') then
--s_dout_R <= dout(0);
dout(2 downto 0) <= dout(3 downto 1);
-- shift left
elsif(rising_edge(clk) and sL = '1') then
--s_dout_L <= dout(3);
dout(3 downto 1) <= dout(2 downto 0);
end if;
end if;
end process;
end arch;