khacvu1092
Newbie level 1
Hi everybody,
I designed a coupled-capacitor instrument amplifier, the output of this amplifier will be sampled and converted to digital code by a SAR-ADC. As we know, the inputs of SAR-ADC VIP, VIN must be the same common voltage level (900mV for Vref=1.8V). Everything is OK when running pre-layout simulation. The problem is when running post-layout simulation, the output of the amplifier VOP, VON (also be VIP, VIN of ADC) have some offset voltage (their common voltage levels are different).
I try using HPF (capacitor series with pseudo-resistor like following figure)
VCMP, VCMN will be connected to 900mV, pseudo-resistor using NMOS has TeraOhm. But it can not equalize the output also.
Do you guys know how to resolved this problem ?
Regards,
I designed a coupled-capacitor instrument amplifier, the output of this amplifier will be sampled and converted to digital code by a SAR-ADC. As we know, the inputs of SAR-ADC VIP, VIN must be the same common voltage level (900mV for Vref=1.8V). Everything is OK when running pre-layout simulation. The problem is when running post-layout simulation, the output of the amplifier VOP, VON (also be VIP, VIN of ADC) have some offset voltage (their common voltage levels are different).
I try using HPF (capacitor series with pseudo-resistor like following figure)
VCMP, VCMN will be connected to 900mV, pseudo-resistor using NMOS has TeraOhm. But it can not equalize the output also.
Do you guys know how to resolved this problem ?
Regards,