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# enhance Rds of a NMOS transistor

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##### Full Member level 2
hello
what techniques can enhance Rds of a NMOS?
Is there any circuit can multiply it by power of ten?

If by enhance you mean increase, cascoding will multiply the resistance looking into the drain by (roughly) the instrinsic gain (gm/gds) of the cascode device

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### travulous

Points: 2
The question is not well formulated.

A simple answer is - decrease the gate width 10x, your Rdson will increase 10x.

travulous

### travulous

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@timof: thanks, but I mean increasing Rds with no change in width of transistor.

... and without changing Vg (Vgs) or Vds voltages?

First Rds under active region and linear region will be quite different. Higher Rds in active region can be achieved than linear region.

in active region , no in ohmic region
no without changing in Vg directly with an special circuit structure like cascode that dgani suggested

Supposing Vds is constant, Mos will change from linear region to active region as Vgs decreases.
As result, output resistance rds will increase.

@leo_o2: dont want to change operation region, suppose MOS is in active region and I want increase Rds of a MOS when it is in active region

Rds=1/(λ.Id). λ is inverse proportional to L. So increasing L will increase Rds.
And reducing Vgs will reduce Id, and it leads to bigger Rds.

@leo_o2: I know this equation but I want a circuit structure for doing this, for example structures like cascode structure that dgnani suggested

If so, pls use a high-gain opamp to drive cascode transistor. It is called gain boosting.

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@leo_o2: thanks, do you have any schematic circuit of this? (gain boosting)

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Thanks leo for your quick reply, is it possible for you, describe me the operation of gain boosting circuit and how it can increase Rsd of MOS?

Pls do small-signal analysis. Then you can find the equavilent Ro is amplified by A.gm2.ro2.
Here, A is the OP gain, gm2.ro2 is the gain from cascode transistor.

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Perhaps I misunderstand the schematic? If the drain of the upper transistor is the output node. then feeding back this voltage will reduce the output impedance, I think.

Points: 2
Leo you mean that the parameter is given in the picture that i attached? for small-signal analysis what model can be used for Op-amp?
Isnt there any feedback technique that doing same operation?

I think, this circuit should do:

Perhaps I misunderstand the schematic? If the drain of the upper transistor is the output node. then feeding back this voltage will reduce the output impedance, I think.

true

I think, this circuit should do:

correct again, i guess getting to level 68 (!) means something...

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