I am having similar problem
Step1:
# Open a new database named foo
db_open foo
# Set some variables to define how ELC does its stuff
set_var EC_SPICE_SIMPLIFY true
set_var EC_HALF_WIDTH_HOLD_FLAG true
set_var EC_SIM_NAME "Spectre"
set_var EC_SIM_TYPE "Spectre"
set_var EC_SPICE_SUPPLY1_NAMES "vdd"
set_var EC_SPICE_SUPPLY0_NAMES "gnd"
# run through the steps that read and parse the subckt file (defined
# in elccfg), and extracts the functionality of each cell
db_prepare -force
db_gate
db_close
exit
-------------------------------------------------------------------------------------------------
Step2:
# open the database you used in step1
db_open foo
# Remove the next 3 lines to use the ipsd/ipsc
# deamons for load balancing on multiple machines
set_var EC_SIM_USE_LSF 1
set_var EC_SIM_LSF_CMD ""
set_var EC_SIM_LSF_PARALLEL 10
# set up some things that let ELC know how to proceed
set_var EC_SIM_NAME "Spectre"
set_var EC_SIM_TYPE "Spectre"
set_var EC_SPICE_SUPPLY1_NAMES "vdd"
set_var EC_SPICE_SUPPLY0_NAMES "gnd"
set_var EC_HALF_WIDTH_HOLD_FLAG true
# run spice (Spectre in this case) to do the actual characterization
db_spice -s Spectre -p typical -keep_log
db_close
exit
----------------------------------------------------------------------------------------------------
elccfg file:
SETUP = "setup.ss"
PROCESS = "typical"
MODEL = "ami_c5n_typ.scs"
SUBCKT = "dut.scs"
----------------------------------------------------------------------------------------------------
gut.scs file:
// Library name: UofU_Digital_Parts
// Cell name: INVX1
// View name: analog_extracted
subckt INVX1 A Y vdd gnd
\+1 (Y A vdd vdd) ami06P w=6e-06 l=6e-07 as=9e-12 ad=9e-12 ps=9e-06 \
pd=9e-06 m=1 region=sat
\+0 (Y A gnd gnd) ami06N w=3e-06 l=6e-07 as=4.5e-12 ad=4.5e-12 ps=6e-06 \
pd=6e-06 m=1 region=sat
ends INVX1
// End of subcircuit definition.
// Library name: UofU_Digital_Parts
// Cell name: NAND2X1
// View name: analog_extracted
subckt NAND2X1 A B Y vdd gnd
\+3 (vdd B Y vdd) ami06P w=6e-06 l=6e-07 as=5.4e-12 ad=9e-12 \
ps=1.8e-06 pd=9e-06 m=1 region=sat
\+2 (Y A vdd vdd) ami06P w=6e-06 l=6e-07 as=9e-12 ad=5.4e-12 \
ps=9e-06 pd=1.8e-06 m=1 region=sat
\+1 (Y B _6 gnd) ami06N w=6e-06 l=6e-07 as=2.7e-12 ad=9e-12 ps=9e-07 \
pd=9e-06 m=1 region=sat
\+0 (_6 A gnd gnd) ami06N w=6e-06 l=6e-07 as=9e-12 ad=2.7e-12 ps=9e-06 \
pd=9e-07 m=1 region=sat
ends NAND2X1
// End of subcircuit definition.
-------------------------------------------------------------------------------------------------------------------
PROBLEM AFTER Step2
elc> #Run as: /Cadence/ETS/tools/elc/bin/32bit/elc -S step2
#INFO: Hostname: Arvind.Dell Login ID: root Date: 2013-04-30 23:47:55 (2013-04-30 18:17:55 GMT)
--------------------------------------------------------------------------------------------------
Encounter - Library Characterizer - Version v10.10-p001_1 - linux_x86 32-bit (12/01/2010 02:45:03)
--------------------------------------------------------------------------------------------------
[2000-2010]Cadence Design Systems, Inc. All rights reserved.
This work may not be copied, modified, re-published, uploaded, executed, or
distributed in any way, in any medium, whether in whole or in part, without
prior written permission from Cadence Design Systems, Inc.
set_var MANPATH = /Cadence/ETS/share/elc/man
elc> # open the database you used in step1
elc> db_open foo
Database : foo is now opened
elc>
elc> # Remove the next 3 lines to use the ipsd/ipsc
elc> # deamons for load balancing on multiple machines
elc> set_var EC_SIM_USE_LSF 1
set_var EC_SIM_USE_LSF = 1
elc> set_var EC_SIM_LSF_CMD ""
set_var EC_SIM_LSF_CMD =
elc> set_var EC_SIM_LSF_PARALLEL 10
set_var EC_SIM_LSF_PARALLEL = 10
elc>
elc>
elc> # set up some things that let ELC know how to proceed
elc> set_var EC_SIM_NAME "Spectre"
set_var EC_SIM_NAME = Spectre
elc> set_var EC_SIM_TYPE "Spectre"
set_var EC_SIM_TYPE = Spectre
elc> set_var EC_SPICE_SUPPLY1_NAMES "vdd"
set_var EC_SPICE_SUPPLY1_NAMES = vdd
elc> set_var EC_SPICE_SUPPLY0_NAMES "gnd"
set_var EC_SPICE_SUPPLY0_NAMES = gnd
elc> set_var EC_HALF_WIDTH_HOLD_FLAG true
set_var EC_HALF_WIDTH_HOLD_FLAG = true
elc>
elc> # run spice (Spectre in this case) to do the actual characterization
elc> db_spice -s Spectre -p typical -keep_log
[WARNING(db_spice)]License for paralled mode is not found. Entering non-parallel mode
DESIGN PROCESS #ID STATUS IPDB
-------------+-------------+----------+--------------+-----------
INVX1 typical D0000 SIMULATE foo
INVX1 typical D0001 SIMULATE foo
============|=============|=============|==========|==============
INVX1 typical 2 2 foo
NAND2X1 typical D0000 SIMULATE foo
NAND2X1 typical D0001 SIMULATE foo
NAND2X1 typical D0002 SIMULATE foo
NAND2X1 typical D0003 SIMULATE foo
NAND2X1 typical D0004 SIMULATE foo
NAND2X1 typical D0005 SIMULATE foo
NAND2X1 typical D0006 SIMULATE foo
NAND2X1 typical D0007 SIMULATE foo
============|=============|=============|==========|==============
NAND2X1 typical 8 8 foo
--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*--*
2013-04-30 23:47:56 (2013-04-30 18:17:56 GMT) : Vectors Launched 10/10
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
Simulation Summary
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
-------------+-------------+----------+--------------+-----------
-------------+-------------+----------+------------+-----------+------------
DESIGN | PROCESS | #ID | STAGE | STATUS | IPDB
-------------+-------------+----------+------------+-----------+------------
INVX1 typical D0000 UNEXPECTED (-5)FAIL foo
INVX1 typical D0001 UNEXPECTED (-5)FAIL foo
NAND2X1 typical D0000 UNEXPECTED (-5)FAIL foo
NAND2X1 typical D0001 UNEXPECTED (-5)FAIL foo
NAND2X1 typical D0002 UNEXPECTED (-5)FAIL foo
NAND2X1 typical D0003 UNEXPECTED (-5)FAIL foo
NAND2X1 typical D0004 UNEXPECTED (-5)FAIL foo
NAND2X1 typical D0005 UNEXPECTED (-5)FAIL foo
NAND2X1 typical D0006 UNEXPECTED (-5)FAIL foo
NAND2X1 typical D0007 UNEXPECTED (-5)FAIL foo
-------------+-------------+----------+------------+----------
[INFO(db_spice)] Check the encounterlc.log/<ipdb_name>/<DESIGN>_<PROCESS>_<ID>.log file to determine the cause of the failure. The SPICE simulation log file can be found in the /Cadence/workdell/encounterlc.work/<DESIGN>_<PROCESS>_<ID>/ directory.
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
- Total Simulation : 10
- Total Passed : 0(0.00%)
- Total Failed : 10(100.00%)
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
elc> db_close
Database : foo is closed
elc> exit
Memory : 3.02M
Time : 5.32 (user), 0.07 (sys), 5.39 (cpu), 5.71 (real)
-----------------------------------------------------------------------------------------------------------------------
encounterlc.log file is generated during step2 execution and deleted automatically at the last, I do not understand what is wrong.
Please let me know any solution for this
Thanks