Hi,
The parameters which u r described that all comes from the front end (After completion of successful synthesis then they will generate constraints file called timing constraint file[.sdc format] which consist the all parameters mentioned by u).
The "sroute" we have to do before clock tree synthesis or after the floorplan & powerplan and i think there is no relation with the CTS and the clock parameters.
"sroute" will routes the block pins, pad pins, pad rings, standard cell pins, and unconnected stripes.
hope this may help u to solve ur problem.
Prashant