enable button, shutting down the whole circuit

[geozog86]

Hello!

I am trying to create a "ON OFF" button for my circuit, so that i can shut it down and i don't consume any power.

The problem is that this part of the design for example, thx to shutting down the biasing, i get A at VDD, and C (due to no current in the small amplifier) also at VDD. But B remains like 20mV below VDD, and the top transistor, even though having Vgs=0, conducts approx half a uA!!! I tried adding a small transistor (pmos with drain on B) but still that small current remains. I tried an nmos (drain on D) But still i have that small current.

Is there any way i can shut it down completely? Or it's an order of magnitude of current that i have to survive with?

(tota budget of current 100uA, this branch 1uA in normal operation, 0.5uA in "OFF"!!)

thx

 

[dgnani]

Expected leakage will depend on technology, supply and size; it definitely seems too high: can you provide us with a more detailed schematic of this branch? e.g. where are the body terminals connected to?

 

[geozog86]

This is the situation with my "OFF" state, all the details, gate currents zero (aA level).

 

[dgnani]

Very surprising: to debug this I suggest
- check that your simulator accuracy is high (and that you are using a full analog simulator)
- run a simulation of this PMOS alone to characterize its subthreshold leakage (plot with log current scale and sweep Vgs at the circuit Vds)
- check your simulation temperature
- check that source and drain currents are (practically) the same

Let us know...

 

[leo_o2]

What's pmos and what process did you use?

 

[geozog86]

ok i'll check all those on Monday......
What i remember is that
--i always check on transient the conservative simulation, so i guess this is pretty accurate
--this sim is for fast corner, 85 degrees, cause it's my worst case as fas as power consumption is concerned
--source and drain currents were the same that's why i didn't write them on the graph

--The process is quite old (0.6um)
--In this process the pmos is the Low Vthreshold model, pmos with body.

For all the rest, i will simulate on monday again, i cannot from home. Have a nice weekend

 

[leo_o2]

Some low vth mosfet will have a current leakage when Vgs=0.
Deplete MOSfet will have current always when Vgs=0.
What's the mosfet Vth?