emulation and timing not met in FPGA

[sun_ray]

Suppose we are running emulation with FPGA and find the timing of 550 MHz is not meeting on FPGA. What can we do then to do the emulation?

 

[shaiko]

If the purpose of your FPGA design is only functional verification - why do you insist on running at such a high frequency?
Just synthesize your final design on the FPGA and make sure it functions properly. Than do a thorough timing analysis on your ASIC synthesis tool.

With your RTL code being the same, everything should work properly.