Emulating the "in system memory conter editor" of altera quartus ii

[flote21]

Hello everbody,

I am in a very big project with an ALTERA FGPA Cyclone IV. This FPGA is going to control several systems and every system has its own configuration file sent by SPI protocol which it is already implemented like a VHDL module in the FPGA. In the start up of the system, the FPGA is sending the intial configuration file for a default hardware which is the most commun. This configuration file is stored in a FIFO memory with the possibility to be modified "on fly" thanks to the "IN SYSTEM MEMORY CONTER EDITOR" tool provided by Quartus II SW. So if the Hardware changed we can use this tool to change the initial configuration SPI file....

But we don't want to use this tool and we want to change the initial SPI config file in the FIFO using the a command recevied by ethernet protcol (The FPGA has also implemented a Ethernet module to communicate with a PC). This command is going to be read by the FGPA and accordint to this we will change the initial configuration file.

See below the instantation of the FIFO memory:

 i_SPI_INIT_RAM : entity WORK.SPI_INIT_RAM
    generic map (
      ADDR_SIZE => SPI_MEM_SIZE,
      DATA_SIZE => SPI_MEM_RDOUT'length,
      INIT_FILE => "../fit/SPI_INIT_RAM.mif",
      INST_NAME => "SPIF"
    )
    port map (
      clock    => CLK            ,
      wren      => '0',
      address => SPI_MEM_ADDR,
      data      => (others => '0'),
      q        => SPI_MEM_RDOUT
    );

As you can see there is a GENERIC ==> "INIT_FILE" where you have to indicated the path of the file you want to load. And it is this path what I want to modify "on fly" when I receive the ethernet command...

Any idea how to implement this?

Thanks.

 

[FvM]

The "in-system memory content editor" hasn't to do with init file functionality. The init file loads the RAM content from configuration bit stream at boot time. The content editor is an IP block that connects one port of a dual port RAM to the virtual JTAG hub.

Starting with Quartus 13, Altera has introduced a feature to drive the virtual JTAG chain from an internal endpoint in the FPGA fabric. It could be basically used to achieve what you want. More easily, you can access one RAM port to read and write the content.

 

[flote21]

Hi! thank you very much for yor answer. But the oly problem that I observe to ths solution: "More easily, you can access one RAM port to read and write the content" is when I power
off/on the system, the RAM will load the init file indicated in the
generic. And what I would like to keep the last file loaded. Is there
any other possible solution for this?

Thanks

The "in-system memory content editor" hasn't to do with init file functionality. The init file loads the RAM content from configuration bit stream at boot time. The content editor is an IP block that connects one port of a dual port RAM to the virtual JTAG hub.

Starting with Quartus 13, Altera has introduced a feature to drive the virtual JTAG chain from an internal endpoint in the FPGA fabric. It could be basically used to achieve what you want. More easily, you can access one RAM port to read and write the content.

 

[FvM]

Obviously you need non-volatile memory to keep the data. E.g. SPI or I2C interfaced EEPROM or flash.

 

[flote21]

Hi FvM, thanks for your answer.

Yes I agree with that. But I have not designed the board and I don't know if this is possible. See picture attached to check the connection between the flash and the FPGA. On the other hand, if I could programm a non-volatile memory to keep the data in the flash. Could you provide me more information about that? or could you give some tips to seach this option in internet?

Thanks.

Obviously you need non-volatile memory to keep the data. E.g. SPI or I2C interfaced EEPROM or flash.

 

[FvM]

Presumed the serial flash in your schematic is acting as configuration memory in active serial mode, you can use the free memory sectors for other purposes, e.g. to store code of soft processors or user data.

Quartus has an alt_asmi IP to read and write configuration flash data.

Cyclone IV will operate the configuration flash only in single bit mode, in so far the connection of quad mode data lines is probably useless.

 

[flote21]

Sorry I dont get it. What do you mean with: "Cyclone IV will operate the configuration flash only in single bit mode, in so far the connection of quad"

Should I have to change anything in the schematic to write code in the flash using the IP al_asmi??

Thanks!

Presumed the serial flash in your schematic is acting as configuration memory in active serial mode, you can use the free memory sectors for other purposes, e.g. to store code of soft processors or user data.

Quartus has an alt_asmi IP to read and write configuration flash data.

Cyclone IV will operate the configuration flash only in single bit mode, in so far the connection of quad mode data lines is probably useless.

 

[FvM]

I mean that some flash pins won't be used.