shaiko
Advanced Member level 5
Code:
process ( clock ) is
begin
if rising_edge ( clock ) then
Q1 <= D ;
end if ;
end process ;
process ( clock ) is
begin
if fallng_edge ( clock ) then
Q2 <= D ;
end if ;
end process ;
Q_DDR <= Q1 or Q2 ;
1.Any reason for the above not to work in an FPGA ?
2.Is there a syntax to describe a VHDL DDR flip flop ?
For example, I know that the following won't work :
Code:
if rising_edge ( clock ) or falling_edge ( clock ) then
Q_DDR <= D ;
end if ;
neither wil
Code:
if rising_edge ( clock ) then
Q_DDR <= D ;
elsif falling_edge ( clock ) then
Q_DDR <= D ;
end if ;
But why ?
Both of the above describe the behavioral model of a DDR flip flop.