EMI reduction design/layout techniques inside chip

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hung_wai_ming@hotmail.com

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emi reduction

Anyone has experience how to reduce EMI or increase EMC for a chip design?
I would like to know any circuit can be built inside chip to reduce.
 

What I know:

1) package design;

2) SSC: spread spectrum clocking.
 

if you have voltage headroom, you can use LDO or series regulator to reduce the EMI seen from the power supply line. Moreover, you can even design on chip EMI filter according to your specification.

regards,


Junfeng
 

Hi Junfeng,

i have considered on-chip EMI filter. But looks like the LC value is too large to be able to integrate.
 

Indeed, with large cap and inductor it is always not easy to integrate. Can you talk more about your EMI specs ?

regards,

Junfeng
 

Isolating sensitive circuitry with digital part
 

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